VC Formal

Features and Benefits

• Assertion-Based Property Verification (FPV): Formal proof-based techniques to verify SystemVerilog Assertion (SVA) properties to ensure correct operation across all possible design activity even before the simulation environment is available. Advanced assertion visualization, property browsing, grouping and filtering allows simple concise access to results.

• Automatic Extracted Property Checks (AEP): Automatic functional analysis for out of bound arrays, arithmetic overflow, X-assignments, simultaneous set/reset, full case, parallel case, multi driver/conflicting bus and floating bus checks without the need for dedicated tests.

• Formal Coverage Analysis (FCA): Complementing simulation flows, VC formal provides proof that uncovered points in coverage goals are indeed unreachable, allowing them to be removed from further analysis—saving significant manual effort.

• SoC-level Connectivity Checking (CC): Verification of connectivity at the SoC level. Flexible input format ensures ease of integration. Powerful debugging, including value annotation, schematic viewing, source code browsing and analysis reporting speeds analysis. Automatic root-cause analysis of unconnected connectivity checks saves significant debug time.

• Sequential Equivalency Checking (SEQ): This allows comparison of designs, after register retiming, insertion of clock gating for power optimization or microarchitecture changes.

• Formal Navigator (NAV): Enables debug and “what-if-analysis” with only the RTL design in the Unified Verdi GUI with/without assertions or Testbench.

• Register Verification (FRV): Helps to formally verify behavior of configuration registers for respective attributes like “read only”, “read/write” or “reset value” eliminating the need for directed tests.

• Formal Testbench Analyzer with Certitude Integration (FTA): Certitude™ provides the unique capability to assess the quality of formal environment. The native integration of Certitude with VC Formal provides meaningful property coverage measurements as part of formal signoff, and identifies any weaknesses such as missing or incorrect properties or constraints. The native integration delivers 5-10X faster performance compared to stand-alone fault injection methods.

• Security Verification (FSV): Helps formally verify that secure data should not reach non-secure destinations and ensures data integrity, where non-secure data should not over-write (or reach) secure destinations.

• Assertion IP (AIP): High performance and optimized assertion IP for verification of standard bus protocols, and usable in Synopsys VC Formal solution and VCS simulation.

• Advanced Debug and Interactivity: Advanced debugging interface built on Unified Verdi GUI based RTL and waveform visualization solutions, including schematic value annotation, on the fly assertion and constraint editing, proof progress feedback, and cone of influence analysis allows users greater visibility and control.

• Formal Scoreboard: Exhaustively verifies the data integrity of data path designs. Ensures that data is transported through the design without being lost, re-ordered, corrupted or duplicated.

• Formal Coverage: Advanced technologies enable formal metrics and methodology to achieve signoff for property verification.