VC Formal

Next-Generation Formal Verification

SoC design complexity demands newer and better verification methods to accelerate verification and debug, as well as reduce overall schedule duration and improve schedule predictability. VC Formal next-generation formal verification has the capacity, speed and flexibility to verify some of the most difficult SoC design challenges, and includes excellent analysis, filtering and debug techniques to quickly identify root causes. In addition, when applied early in the design schedule, before simulation is available, overall schedule improvements can be realized.

VC Formal

Features and Benefits

  • Assertion-Based Verification: Formal proof-based techniques to verify SVA properties or assertions to ensure correct operation across all possible design activity – even before the simulation environment is available. Advanced assertion visualization and property browsing, grouping and filtering allows simple concise access to results.

  • Advanced Debug: Advanced debugging interface built on industry standard Verdi-based RTL and waveform visualization solutions, including schematic value annotation for connectivity checking.

  • Interactivity: On the fly assertion and constraint editing, proof progress feedback, and cone of influence analysis allows users excellent visibility and control.

  • SoC-level Connectivity Checking: Verification of connectivity at the fullchip SoC level. Flexible input format ensures ease of flow integration. Powerful debugging, including value annotation, schematic viewing, source code browsing and analysis reporting speeds analysis. Automatic root-cause analysis of unconnected connectivity checks saves significant debug time.

  • Sequential Equivalency Checking: This allows comparison of designs, even after insertion of power gating, or microarchitecture changes.

  • Formal Coverage Analysis: Complementing simulation flows, formal technologies can provide proof that uncovered points in coverage goals are indeed unreachable, allowing these to be removed from further analysis— saving manual effort.

  • Certitude Integration: Certitude provides unique information to assess the formal environment. Integrated with VC Formal, Certitude can provide meaningful property coverage measurements within the formal environment as part of the formal IP signoff, and can identify any weaknesses in the formal environment such as missing or incorrect properties or constraints.

  • Formal Scoreboard: Exhaustively verifies the data integrity of data path designs. Ensures that data is transported through the design without being lost, re-ordered, corrupted or duplicated.