Cloud native EDA tools & pre-optimized hardware platforms
SoC design complexity demands fast and comprehensive verification methods to accelerate verification and debug, as well as shorten overall schedule and improve predictability. The VC Formal™ next-generation formal verification solution has the capacity, speed and flexibility to verify some of the most complex SoC designs and includes comprehensive analysis and debug techniques to quickly identify root causes leveraging Verdi® debug platform. The VC Formal solution consistently delivers highest performance and capacity, with more design bugs found, more proofs on larger designs and achieves faster coverage closure through the native integration with VCS® functional verification solution.
Synopsys also offers Formal Verification Services specializing in enhancing productivity and reducing risk by working closely with domain experts in the deployment of verification methodology.
The VC Formal solution includes a comprehensive set of formal applications (Apps), including Formal Property Verification (FPV), Automatic Extracted Properties (AEP), Formal Coverage Analyzer (FCA), Connectivity Checking (CC), Sequential Equivalence Checking (SEQ), Formal Register Verification (FRV), Formal X-Propagation Verification (FXP), Formal Testbench Analyzer (FTA), Regression Mode Accelerator (RMA), Datapath Validation (DPV), Functional Safety (FuSa) and a portfolio of Assertion IPs (AIP) for verification of standard bus protocols.