Next-Generation Formal Verification
SoC design complexity demands fast and comprehensive verification methods to accelerate verification and debug, as well as shorten overall schedule and improve predictability. The VC Formal™ next-generation formal verification solution has the capacity, speed and flexibility to verify some of the most difficult SoC design challenges, and includes comprehensive analysis and debug techniques to quickly identify root causes in the Verdi® debug platform. The VC Formal solution consistently delivers higher performance and capacity, with more bugs found, more proofs on larger designs and achieves faster coverage closure through the native integration with VCS® functional verification solution.
The VC Formal solution includes a comprehensive set of formal applications (Apps), including Property Verification (FPV), Auto Extracted Properties (AEP), Coverage Analyzer (FCA), Connectivity Checking (CC), Sequential Equivalence Checks (SEQ), Register Verification (FRV), Testbench Analyzer (FTA), Formal Navigator (NAV) and a portfolio of Assertion IPs (AIP) for verification of standard bus protocols.