Cloud native EDA tools & pre-optimized hardware platforms
SoC design complexity demands fast and comprehensive verification methods to accelerate verification and debug, as well as shorten overall schedule and improve predictability.
Leveraging the latest formal technologies and Machine Learning techniques, Synopsys VC Formal™ has the capacity, speed and flexibility to exhaustively verify some of the most complex SoC designs, find deep corner-case design bugs, and achieve formal signoff. Natively integrated with Synopsys VCS®, Verdi®, VC SpyGlass™, VC Z01X Fault Simulation and other Synopsys design and verification solutions, VC Formal continues to innovate to solve the toughest verification challenges in the industry.
Synopsys also offers Formal Verification Services specializing in enhancing productivity and reducing risk by working closely with domain experts in the deployment of verification methodology.
Innovative formal engines and ML-based orchestrations find more bugs and achieve more proofs on larger designs
Exhaustive formal analysis catches corner-case bugs and enables formal signoff for control and datapath blocks
Easy-to-use formal apps, native integration with VCS and Verdi, and Formal Consulting Services reduce formal adoption effort
Automatic functional analysis for out of bound arrays, arithmetic overflow, X-assignments, simultaneous set/reset, full case, parallel case, multi driver/conflicting bus and floating bus checks without the need for dedicated simulation tests.
Complementing simulation flows, VC formal provides proof that uncovered points in coverage goals are indeed unreachable, allowing them to be removed from further analysis—saving significant manual effort.
Checks for unknown signal value (X) propagation through the design and allows tracing of the failed property to source of X in the Verdi schematic and waveform.
Verification of connectivity at the SoC level. Flexible input format ensures ease of integration. Powerful debugging, including value annotation, schematic viewing, source code browsing and analysis reporting speeds analysis. Automatic root-cause analysis of unconnected connectivity checks saves significant debug time.
Helps to formally verify behavior of configuration registers for respective attributes like “read only”, “read/write” or “reset value” eliminating the need for directed simulation tests.
This allows comparison of designs, after register retiming, insertion of clock gating for power optimization or microarchitecture changes.
Formal proof-based techniques to verify SystemVerilog Assertion (SVA) properties to ensure correct operation across all possible design activity even before the simulation environment is available. Advanced assertion visualization, property browsing, grouping and filtering allow simple concise access to results. Formal navigator enables debug and "what-if-analysis" with only the RTL design in the Unified Verdi GUI with/without assertions or Testbench.
Helps formally verify that secure data should not reach non-secure destinations and ensures data integrity, where non-secure data should not over-write (or reach) secure destinations.
Provides significant performance improvement to formal property verification using Machine Learning technology. Use of this app accelerates formal property verification to achieve better convergence of formal proofs for subsequent runs and enables significant saving of compute resources in nightly formal regressions.
Testbench Quality Assurance provides the unique capability to assess the quality of formal environment. The native integration of Testbench Quality Assurance with VC Formal provides meaningful property coverage measurements as part of formal signoff and identifies any weaknesses such as missing or incorrect properties or constraints. The native integration delivers 5-10X faster performance compared to stand-alone fault injection methods.
Integrated HECTOR™ technology within VC Formal and contains custom optimizations and engines for datapath verification (ALU, FPU, DSP etc.) using transaction level equivalence. This app leverages the Verdi graphical user interface for debug.
Functional safety verification is an essential requirement for automotive SoC and IP designs. This App formally identifies and classifies faults based on observability or detectability criteria. Complementing fault simulation with Z01X™, the combined solution reduces the effort and time required to achieve the test coverage closure and meet functional safety objectives.
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