Next-Generation Formal Verification
SoC design complexity demands fast and comprehensive verification methods to accelerate verification and debug, as well as shorten overall schedule and improve predictability. The VC Formal™ next-generation formal verification solution has the capacity, speed and flexibility to verify some of the most complex SoC designs and includes comprehensive analysis and debug techniques to quickly identify root causes leveraging Verdi® debug platform. The VC Formal solution consistently delivers highest performance and capacity, with more design bugs found, more proofs on larger designs and achieves faster coverage closure through the native integration with VCS® functional verification solution.
The VC Formal solution includes a comprehensive set of formal applications (Apps), including Property Verification (FPV), Auto Extracted Properties (AEP), Coverage Analyzer (FCA), Connectivity Checking (CC), Sequential Equivalence Checks (SEQ), Register Verification (FRV), X-Propagation Verification (FXP), Testbench Analyzer (FTA), Formal Navigator (NAV), Regression Mode Accelerator (RMA), Datapath Validation (DPV) and a portfolio of Assertion IPs (AIP) for verification of standard bus protocols.