Cloud native EDA tools & pre-optimized hardware platforms
SoC designs use low power design techniques to enable support for advanced power management required in many of today’s electronic products, from mobile devices to servers and networking. Advanced low power techniques such as power gating, retention, low-VDD standby, and dynamic voltage scaling (DVS) employ voltage control to enable fine-grained power management, and are seeing increasing adoption. Due to the nature of low power design architectures and behavior, verification and signoff for low power designs are exponentially more challenging than for always-on designs. The VC LP™ static low power verification solution includes over 650 checks and offers full-chip capacity and performance for complete low power static signoff.
Synopsys also offers Low Power Verification Services specializing in enhancing productivity and reducing risk by working closely with domain experts in the deployment of verification methodology.
VC LP can be run at RTL, post-synthesis and post-P&R and can catch low power bugs earlier and faster than traditional methods. Low power design techniques add new design elements at different stages of the design flow. Architectural design bugs that violate the principles of low power design may exist even at RTL. Isolation cells are typically synthesized automatically, while retention register connections need to be validated after synthesis and again after place and route. Multi-voltage designs require the appropriate power and ground pins to be connected to the specified supply rails. Hence, low power static checking must operate comprehensively in all stages of the design flow to accurately verify correct implementation and behavior. VC LP offers a comprehensive set of checks to achieve this:
In addition, analyzing, debugging and fixing violations must be easy and efficient, to effectively enable designers to eliminate design-killing low power bugs early.