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VC LP
Low Power Signoff and Static Verification
SoC designs use low power design techniques to enable support for advanced power management required in many of today’s electronic products, from mobile devices to servers and networking. Advanced low power techniques such as power gating, retention, low-VDD standby, and dynamic voltage scaling (DVS) employ voltage control to enable fine-grained power management, and are seeing increasing adoption. Due to the nature of low power design architectures and behavior, verification and signoff for low power designs are exponentially more challenging than for always-on designs. The VC LP™ static low power verification solution includes over 650 checks and offers full-chip capacity and performance for complete low power static signoff.
Synopsys also offers Low Power Verification Services specializing in enhancing productivity and reducing risk by working closely with domain experts in the deployment of verification methodology.
Features and Benefits
VC LP can be run at RTL, post-synthesis and post-P&R and can catch low power bugs earlier and faster than traditional methods. Low power design techniques add new design elements at different stages of the design flow. Architectural design bugs that violate the principles of low power design may exist even at RTL. Isolation cells are typically synthesized automatically, while retention register connections need to be validated after synthesis and again after place and route. Multi-voltage designs require the appropriate power and ground pins to be connected to the specified supply rails. Hence, low power static checking must operate comprehensively in all stages of the design flow to accurately verify correct implementation and behavior. VC LP offers a comprehensive set of checks to achieve this:
- Power Intent Consistency Checks: Syntax and semantic checks on UPF that help validate the consistency of UPF prior to implementation. Incorrect power intent will result in incorrect low power design implementation.
- Architectural Checks: Global checks at RTL for signals violating power architecture rules. VC LP validates the design in its entirety and checks the critical signal networks in the design for the various power modes. These checks help find connectivity related bugs, which would cause functional issues very early in the design cycle.
- Structural and Power and Ground (PG) Checks: Validation of insertion and connection of isolation cells, power switches, level shifters, retention registers and always-on cells throughout the implementation flow, from initial synthesis to place and route.
- Functional Checks: Checks the correct functionality of isolation cells and power switches. VC LP offers the most accurate and production-proven support for industry-standard IEEE 1801 Unified Power Format (UPF) power intent.
In addition, analyzing, debugging and fixing violations must be easy and efficient, to effectively enable designers to eliminate design-killing low power bugs early.
- Hierarchical Power State Analysis: Designs with a large number of power domains benefit from the automatic derivation of a hierarchical power-state table. VC LP understands the power intent and can prune many power states to a few distinct ones, thus reducing the effort involved to specify and then verify all the power states, transitions and sequences.
- Complex Power State Table Debug: Related to hierarchical power state analysis, VC LP provides users the ability to understand and if necessary, debug the resulting complex power state tables.
- Powerful Verdi-based Debug: Low power violations in VC LP can be visualized, analyzed and debugged in the familiar and intuitive Verdi® power-aware debug environment.