Next-Generation Low Power Static Checking

SoC designs use low power design techniques to enable support for advanced power management required in many of today’s electronic products, from mobile device to servers and networking. Advanced low power techniques such as Power Gating, Retention, Low-Vdd Standby, and Dynamic Voltage Scaling (DVS) employ voltage control to enable fine-grained power management, and are seeing increasingly prevalent adoption. Due to the nature of low power design architectures and behavior, low power verification complexity is exponentially more challenging than for always-on verification. Native low power simulation and advanced low power static verification and signoff must manage this increased complexity, and still attain all verification objectives.

Static Checking Challenges for Low Power Designs

Advanced intent-driven low power design flows requires complete and rapid checking of low power implementation and behavior validity at every stage in the flow. In addition, analyzing, debugging and fixing violations must be easy and efficient, in order to effectively enable designers to eliminate possibly design-killing low power bugs early in the design flow.
Low power SoC designs are partitioned into power domains that can be separately controlled by one or more low power design techniques, and verification complexity increases exponentially with the number of power domains. Also, increasingly stringent power requirements have necessitated the use of multiple supply voltages, adding another dimension to verification complexity. Finally, low power designs typically operate in multiple modes, with each mode corresponding to one or more power states—yet a third dimension of additional complexity. Comprehensive verification of low power designs requires verification not just in all the power domains, all combinations of supply voltages, and all power states and modes, but also of the specified transitions and transition order within these power states as the design moves from one operating mode to another. A single bug in any of these incredibly complex scenarios may cause functional failures in silicon.
Low power design techniques add new design elements at different stages of the design flow. Architectural design bugs that violate the principles of low power design may exist even at RTL. Isolation cells are typically synthesized automatically. Retention register connections need to be validated after synthesis and again after place and route. Multi-voltage designs require the appropriate power and ground pins to be connected to the specified supply rails. Low power static checking must operate comprehensively in all stages of the design flow in order to accurately verify correct implementation and behavior in all of these cases. 

Features and Benefits

  • Power Intent Consistency Checks: Syntax and semantic checks on UPF that help validate the consistency of UPF prior to implementation. Incorrect power intent will result in incorrect low power design implementation. The UPF consistency checks ensure that the power intent specification driving low power implementation is syntactically and semantically correct.

  • Architectural Checks: Global checks at RTL for signals violating power architecture rules. VC LP validates the design in its entirety and checks the critical signal networks in the design for the various power modes. These checks help find connectivity related bugs, which would cause functional issues very early in the design cycle.

  • Structural and Power and Ground (PG) Checks: Validation of insertion and connection of isolation cells, power switches, level shifters, retention registers and always-on cells throughout the implementation flow, from initial synthesis to place and route.

  • Functional Checks: Checks the correct functionality of isolation cells and power switches. The most accurate and production-proven support for industry-standard IEEE 1801 Unified Power Format (UPF) power intent.

  • Hierarchical Power State Analysis: Designs with a large number of power domains benefit from the automatic derivation of a hierarchical power- state table. VC LP understands the power intent and is able to prune a large number of power states to a few distinct ones, thus reducing the effort involved to specify and then verify all the power states, transitions and sequences.

  • Complex Power State Table Debug: Related to hierarchical power state analysis, VC LP provides users the ability to understand and if necessary, debug the resulting complex power state tables.