Advanced intent-driven low power design flows requires complete and rapid checking of low power implementation and behavior validity at every stage in the flow. In addition, analyzing, debugging and fixing violations must be easy and efficient, in order to effectively enable designers to eliminate possibly design-killing low power bugs early in the design flow.
Low power SoC designs are partitioned into power domains that can be separately controlled by one or more low power design techniques, and verification complexity increases exponentially with the number of power domains. Also, increasingly stringent power requirements have necessitated the use of multiple supply voltages, adding another dimension to verification complexity. Finally, low power designs typically operate in multiple modes, with each mode corresponding to one or more power states—yet a third dimension of additional complexity. Comprehensive verification of low power designs requires verification not just in all the power domains, all combinations of supply voltages, and all power states and modes, but also of the specified transitions and transition order within these power states as the design moves from one operating mode to another. A single bug in any of these incredibly complex scenarios may cause functional failures in silicon.
Low power design techniques add new design elements at different stages of the design flow. Architectural design bugs that violate the principles of low power design may exist even at RTL. Isolation cells are typically synthesized automatically. Retention register connections need to be validated after synthesis and again after place and route. Multi-voltage designs require the appropriate power and ground pins to be connected to the specified supply rails. Low power static checking must operate comprehensively in all stages of the design flow in order to accurately verify correct implementation and behavior in all of these cases.