About VC LP

SoC level low power signoff can generate design size complexities including 100s of power domains, verification of millions of low power states, and architectural complexities that can arise because of IP integration. Synopsys VC LP seamlessly scales to address the SoCs level of complexity, capacity and performance requirements and enables up to 10X speed up in low power signoff from RTL to PG Netlist.  

Synopsys also offers Low Power Verification Services specializing in enhancing productivity and reducing risk by working closely with domain experts in the deployment of verification methodology.

Key Benefits

Billion Gate Capacity Icon | Synopsys VC LP

Billion Gate Capacity​

Faster Turn Around Time Icon | Synopsys VC LP

Faster Turn Around Time

ML-driven Signoff Icon | Synopsys VC LP

ML-driven Signoff

Complete Package Icon | Synopsys Debug, Planning & Coverage

Comprehensive Low Power Verification


The recently expanded VC LP solution includes the Signoff Abstract Model (SAM) based methodology for hierarchical verification plus multi-threading and ML-enabled root cause analysis technology for improved QoR and better debugability. 

Signoff Abstract Model Flow

Up to 10x better capacity with signoff abstract model (SAM) flow

  • Key requirements at the SoC level are faster signoff and improved capacity
  • VC LP delivers SoC level signoff without any loss of accuracy or quality of results (QoR)


Up to 2x runtime improvement with multi-threading

  • Support for using multiple cores
  • Provides 1.5-2x runtime gain without much increase in memory

ML-based Root-cause Analysis

Up to 10x faster debug with machine learning (ML) based root-cause analysis

  • Managing large report volumes for signoff can be slow and error prone
  • VC LP delivers smart grouping so users can fix root-cause violations faster

Comprehensive Low Power Verification

  • Available at the RTL, Netlist and PG netlist stages as part of the low power signoff
  • Signoff at the partition, sub-system and SoC levels


What Our Customers Are Saying

Using the Signoff Abstract Model flow in the VC LP solution enables us to accelerate static low-power verification by 5X, and ensures high-quality QoR and signoff for our ASIC designs. With minimal changes to existing environment configuration, the hierarchical flow can be seamlessly adopted over several designs, effectively supporting the expedition of high-quality ASIC delivery."

Jung Yun Choi


VP at Samsung Electronics

Support and Training


Explore the Synopsys Support Community! Login is required.


Erase boundaries and connect with the global community.