Samsung’s low-power designs used the highly sophisticated low-power SoC design techniques. While these techniques allow for fine-grained power management, they also add complexity to the design and verification processes. Some common low-power techniques in Samsung Foundry designs are listed as below:
- Power Gating & Isolation: The power gating technique implements power switches into the IC design, which requires isolation gates that clamp the boundaries of the power domain to known values when off. A power management unit controls the power switch and isolation by enabling signals to ensure that values during shutdown are clamped to the right values at the right time.
- Retention: Retention is another technique used along with power gating. In each shutdown block, when the block is off, either a subset of the flops or all the flops in the block have their previous values saved. When the block powers on, then the previously saved values are restored. This saves power by reducing the time and steps necessary to get the saved state, as well as improving the overall ramp-up time to restore the previous functionality of the block.
- Level Shifter: Multi-voltage designs require designing in separate voltage islands, meaning that voltage crossings between islands may require “level shifter” cells that implement and analyze the blocks at their different voltage characteristics.
The intricacies of low-power SoC design architectures and elements, such as those discussed above, pose greater challenges for chip verification and approval compared to always-on SoC designs. In fact, SoC-level low-power signoff is orders of magnitude more complex than IP-level verification. This stems from the complexity of design sizes, hundreds of power domains, and millions of low-power states that need to be verified. Additionally, there are the architectural complexities that arise from IP integration, such as functional feedthroughs, feedback loops, and segregation of reports based on IP ownerships.