EDA
System
IP
SolvNetPlus
Training & Education
With the semiconductor industry shifting from monolithic chip designs to multi-die architectures — which leverage chiplets for improved flexibility, scalability, and time to market — engineering teams are facing new hurdles and complexities. Beyond power, performance, and area (PPA), they must now consider die-to-die connectivity, advanced packaging, and even the effects of multiphysics.
This broader scope demands tight collaboration across design, IP, packaging, and manufacturing.
Synopsys and Samsung Foundry are working together to meet these demands. And we’re delivering integrated solutions that help chip developers navigate several converging trends:
- AI and high-performance computing (HPC) workloads demand massive compute density and unprecedented memory bandwidth.
- Yield and cost pressures make large monolithic dies less practical at advanced nodes.
- Time-to-market pressures push teams to reuse IP and design blocks wherever possible.
- System-level constraints spanning power, thermal, and signal integrity now dominate design decisions.
In multi-die designs, every element — from packaging and interconnects to power consumption and thermal behavior — is interdependent. Early-stage planning is essential because decisions made upstream can ripple through the entire design flow.
Innovate Faster with Synopsys Multi-Die Solution
Unlock the secrets to overcoming multi-die design challenges with our comprehensive eBook.
Transitioning from point tools to system-level solutions
We’ve been working closely with Samsung Foundry to create integrated design flows that combine process technology, advanced packaging, IP, and AI-powered EDA tools.
A central focus of the collaboration is system-technology co-optimization (STCO), which extends beyond traditional design-technology co-optimization (DTCO). Instead of optimizing individual blocks in isolation, this approach enables customers to evaluate trade-offs across dies, interconnects, packaging, power delivery, and thermals early in the design cycle.
“Ten years ago, EDA and IP were largely point products,” explains Kevin Yee, senior director of solutions and enablement at Samsung Foundry. “Today, success depends on how well everything works together — from SoC to memory to package. Synopsys has transformed into a systems company, and Samsung Foundry is doing the same by delivering integrated process, packaging, and ecosystem capabilities.”
This system-centric approach is especially critical for newer market entrants. AI startups, automotive companies, and developers focused on edge and embedded applications often lack the resources required for in-house chip design.
“Companies know they need multi-die designs with chiplets, but they don’t always know how to put all the pieces together,” Yee says. “That’s where proven methodologies, automated flows, and strong foundry-EDA collaboration become essential.”
Leveraging AI-powered automation
As multi-die designs become increasingly complex, manual design and validation workflows are neither fast nor scalable enough. AI-powered automation is now vital for accelerating design cycles and improving results. As part of our ongoing collaboration, we’re working with Samsung Foundry to integrate AI across design methodologies — from physical implementation to system-level optimization.
“The biggest benefit we see from AI is speed and quality,” Yee notes. “Things that used to take days or weeks can now be run in hours. Customers can explore more design options, iterate faster, and ultimately achieve better performance and precision.”
This includes AI-powered optimization for thermal behavior, signal and power integrity, and power delivery across the die and package using unified exploration-to-signoff platforms like Synopsys 3DIC Compiler.
“AI isn’t just speeding up design," Yee says. "It’s making it smarter."
Delivering real world results
Our expanded collaboration with Samsung Foundry is already delivering tangible results. Together, we’ve tackled some of the industry’s most complex multi-die design challenges, delivering production-proven solutions across several high-impact projects:
Accelerating AI compute with automated multi‑die design
- What: A successful customer tape-out using SF2P process technology and 2.5D Cube-S advanced packaging.
- How: Enabled by 3DIC Compiler for automated multi-die implementation.
- Impact: Reduced design turnaround time by 50% while improving signal integrity results by 6%, demonstrating how automation can dramatically accelerate and improve complex 3DIC designs.
- Benefit: Faster time to market for AI and HPC customers without sacrificing design quality.
Validating next-generation memory integration
- What: Validation of a 2.5D interposer design integrating SoC, DRAM, and HBM4 PHY as a part of Samsung’s total solution offerings.
- How: 3DIC Compiler was used for automated signal routing across the interposer.
- Impact: Validated readiness for next-generation memory standards, including HBM4 and beyond.
- Benefit: Provides customers with confidence that advanced memory integration is production ready.
Advancing open chiplet interconnect standards
- What: Successful SF4X tape-out validating Synopsys UCIe IP at 32G data rate.
- How: Close foundry–EDA collaboration ensured signal integrity and performance targets were met.
- Impact: Strengthens ecosystem readiness for open, chiplet-based die-to-die connectivity.
- Benefit: Lays the foundation for interoperable chiplet designs and future HBM architectures.
Reducing risk in complex 2.5D and 3D designs
- What: Jointly developed and recommended multi-die design flows.
- How: Uses multiphysics analysis with 3DIC Compiler to assess TSV design, bump planning, and signal integrity.
- Impact: Reduces risk and improves predictability in complex, stacked-die systems.
- Benefit: Helps customers manage complexity while achieving performance and power goals.
Laying the foundation for AI-optimized system design
- What: Early-stage exploration of AI-based system optimization.
- How: Applying machine learning to thermal, power, and signal integrity challenges.
- Impact: Signals a long-term investment in smarter, more adaptive design flows.
- Benefit: Positions customers to tackle future challenges as designs scale in size and complexity.
Enabling system-level innovation at scale
Looking ahead, both companies anticipate system-level frameworks and multi-die designs will expand beyond AI and HPC use cases, with increased adoption across automotive, edge, and consumer applications.
Continued ecosystem collaboration will be critical for adoption. Just as reference flows were co-developed for mobile and automotive, the industry now needs clearer, application-specific flows for multi-die designs.
We’ll continue working closely with Samsung Foundry to enable our mutual customers to evolve and innovate — with greater speed, confidence, and scale.
Continue Reading
World’s First HBM4 IP Test Chip: Early Silicon Validation for Next-Generation AI and HPC
