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DesignWare High-Speed SerDes IP Solutions

Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.

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Latest News

Products +

<p><a href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_112g_ethernet_phy">112G Ethernet PH<span style="font-family: inherit;">Y IP</span></a><span style="font-family: inherit;"> enables true long reach channels for up to 800G high-performance computing SoCs</span></p>
<p><span style="font-family: inherit;"><a href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_56g_ethernet_phy">56G Ethernet PHY IP</a> addresses reach and performance of up to 400G Ethernet applications</span></p>
<p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/die-to-die.html">Die-to-Die PHY IP</a> enables up to 112G XSR connectivity</span></p>
<p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/multiprotocol-phys.html">Multi-Protocol PHYs</a> supports Ethernet, PCI Express, CCIX, CXL and more protocols</span></p>
<p><a href="/content/synopsys/en-us/designware-ip/interface-ip/pci-express.html">PCI Express PHY IP</a> enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes</p>

Comprehensive Portofolio

112G Ethernet PHY IP enables true long reach channels for up to 800G high-performance computing SoCs

56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications

Die-to-Die PHY IP enables up to 112G XSR connectivity

Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols

PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes

Webinars & Whitepapers +

<p>Webinar: <a href="https://www.synopsys.com/designware-ip/resources/webinars/overcoming-pcie6-integration-and-validation-challenges.html?cmp=disp_ip_misc_07_14_22_1549306_wbr_ww_pcie_hhs20">Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges</a></p>
<p>Webinar: <a href="https://attendee.gotowebinar.com/register/1388436214572543504?source=Synopsys">PCIe 6.0 From IP to Interconnect in High-Performance Computing</a></p>
<p>Webinar: <a href="/content/synopsys/en-us/designware-ip/resources/webinars/minimize-latency-with-400g-800g-ethernet-ip.html">Keeping Latency to a Minimum with 400G/800G Ethernet IP</a></p>
<p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1474205&tp_key=82f85b7d37&sti=web">Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution</a></p>
<p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1466672&amp;tp_key=bc58fabe78&amp;sti=search">PCI Express 6.0 Design Considerations & IP Implementation</a></p>
<p>Whitepaper: <a href="https://www.synopsys.com/dw/doc.php/wp/Evolution_of_Data_Center_Networking_Technology-IP_and_Beyond_wp.pdf">Evolution of Data Center Networking Technology — IP and Beyond</a></p>

Educational Content Covering a Wide Range of Topics to Keep You Up-to-Date

Webinar: Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

Webinar: PCIe 6.0 From IP to Interconnect in High-Performance Computing

Webinar: Keeping Latency to a Minimum with 400G/800G Ethernet IP

Webinar: Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution

Webinar: PCI Express 6.0 Design Considerations & IP Implementation

Whitepaper: Evolution of Data Center Networking Technology — IP and Beyond

Videos +

Now Showing: Synopsys 112G Ethernet PHY IP on TSMC N5 Performance Results

PCIe 6.0 End-to-End Hardware Linkup and Performance

Synopsys 112G Multi-Protocol PHY IP and Amphenol 2m DAC & Examax Interoperability

Multi-Vendor Extra Long Reach 112G SerDes Interoperability Between Synopsys and AMD

Synopsys 112G Ethernet IP Interoperating with Optical Components & Equalizing E-O-E Link

Synopsys PCIe 6.0 IP TX and RX Successful Interoperability with Keysight

Latest News +

<p><a href="https://blogs.synopsys.com/from-silicon-to-software/2022/05/12/pcie-5-0-solutions/">Synopsys IP Passes PCIe 5.0 Compliance and Makes Integrators List</a></p>
<p><a href="https://news.synopsys.com/2021-06-01-Synopsys-DesignWare-IP-Achieves-Broad-Industry-Adoption-with-Multiple-First-Pass-Customer-Silicon-Successes-on-TSMCs-N5-Process">Synopsys IP Achieves Broad Industry Adoption on TSMC's N5 Process</a></p>
<p><a href="https://news.synopsys.com/2021-05-04-Synopsys-Completes-Acquisition-of-MorethanIP">Synopsys Completes Acquisition of MoreThanIP</a></p>
<p><a href="https://news.synopsys.com/2021-01-28-Synopsys-Demonstrates-Silicon-Proof-of-DesignWare-112G-Ethernet-PHY-IP-in-5nm-Process-for-High-Performance-Computing-SoCs">Silicon-Proof of 112G Ethernet PHY IP in 5nm Process</a></p>
<p><a href="https://news.synopsys.com/2020-09-24-Synopsys-and-GLOBALFOUNDRIES-Collaborate-to-Develop-Broad-Portfolio-of-DesignWare-IP-for-12LP-FinFET-Solution,1">IP for GF 12LP+ Targeting Cloud Computing and Edge AI SoCs</a></p>
<p><a href="https://news.synopsys.com/2020-08-27-Chelsio-Adopts-Synopsys-DesignWare-56G-Ethernet-PHY-IP-to-Accelerate-Development-of-High-Performance-Computing-SoC">Chelsio Adopts DesignWare 56G Ethernet PHY IP for HPC Design</a></p>
<p><a href="https://news.synopsys.com/2020-05-11-Synopsys-Accelerates-High-Performance-Computing-SoC-Designs-with-Industrys-Broadest-IP-Portfolio-for-TSMCs-5nm-Process-Technology">High-Performance Computing IP for TSMC's 5nm Process</a></p>

Stay Current with the Latest News on High-Speed SerDes IP

Synopsys IP Passes PCIe 5.0 Compliance and Makes Integrators List

Synopsys IP Achieves Broad Industry Adoption on TSMC's N5 Process

Synopsys Completes Acquisition of MoreThanIP

Silicon-Proof of 112G Ethernet PHY IP in 5nm Process

IP for GF 12LP+ Targeting Cloud Computing and Edge AI SoCs

Chelsio Adopts DesignWare 56G Ethernet PHY IP for HPC Design

High-Performance Computing IP for TSMC's 5nm Process

Featured Resources

Blog

How Does Short-Reach Connectivity Transcend Physical and Power Limits?

Blog

A Primer on Chip Packaging for Multi-Die Designs

Article

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications

Article

Very Short Reach (VSR) Connectivity for Optical Modules

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