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DesignWare High-Speed SerDes PHYs

Synopsys provides a comprehensive portfolio of high-speed SerDes PHY IP with leading power, performance, and area to help designers meet their long and short reach connectivity requirements in up to 800G high-performance computing SoCs for hyperscale data center, networking, and AI applications. Let Synopsys, the most trusted IP provider, help you with your next SoC design requiring high-speed SerDes PHY IP in advanced FinFET processes.

112G Ethernet PHY IP

Enables true long reach channels for up to 800G high-performance computing SoCs

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56G Ethernet PHY IP

Addresses reach and performance of up to 400G Ethernet applications

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Die-to-Die PHY IP

Enables ultra- and extra-short reach (USR/XSR) connectivity for up to 112G data rates

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Multi-Protocol PHYs

Support up to 32G PCI Express, CCIX, CXL, Ethernet, and more protocols

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Webinar: Ensuring Known Good Dies in SiPs with Die-to-Die PHY IP

Use cases for splitting complex SoCs into multiple dies are growing due to advantages such as scalability, flexibility, and total system cost. As several dies are integrated into a single package, the cost of only detecting a defective die after the package assembly can become very significant. For SiPs it is critical to be able to identify and assemble only the known good dies (KGDs) in a package. To achieve this goal, high-performance computing (HPC) SoC designers must leverage the SerDes-based USR/XSR or parallel-based HBI die-to-die PHY IP solution that offers testability features with extended test coverage at the die and link level. Attend this webinar to learn about: How testability features in die-to-die PHY IP enable test coverage for identifying KGDs and extending test coverage across all dies with die-to-die PHY IP.

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Choosing the Right IP for Die-to-Die Connectivity

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DesignWare High-Speed SerDes PHYs

112G Ethernet PHY IP

56G Ethernet PHY IP

Die-to-Die PHY IP

Multi-Protocol PHYs

Webinar: Ensuring Known Good Dies in SiPs with Die-to-Die PHY IP

Synopsys provides designers with a comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast integration of the high-speed SerDes PHY IP into SoCs.

112G SerDes Reliability

IP for GF 12LP+ Targeting Cloud Computing and Edge AI SoCs

Accurate Modeling and Integration Considerations for 112G SerDes PHY IP

SemiWiki: Parallel Based PHY IP for Die-to-Die Connectivity

Chelsio Adopts DesignWare 56G Ethernet PHY IP for HPC Design

Production Test of System-in-Package with Die-to-Die PHY IP

The New Frontier of Die-to-Die Interface IP

High-Speed SerDes At 7/5nm

High-Performance Computing IP for TSMC's 5nm Process

Leveraging IP to Enable Reliable Die-to-Die Connectivity

Inomize Selects Synopsys' Silicon-Proven 56G Ethernet PHY IP

56G/112G Ethernet and Die-to-Die PHY IP Essentials

Die-To-Die Connectivity

SemiWiki: Synopsys’ New Die-to-Die PHY IP – What It Means

SemiWiki: High-Speed PHY IP for Hyperscale Data Centers

Shift from NRZ to PAM-4 Signaling for 400G Ethernet

New Challenges for Data Centers

Hyperscale to the Rescue: To 800G and Beyond

Choosing the Right IP for Die-to-Die Connectivity

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