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DesignWare High-Speed SerDes PHY IP Solutions
Synopsys' comprehensive portfolio of high-speed SerDes PHY IP with leading power, performance, latency and area, allows designers to meet the long and short reach connectivity requirements of 100G, 200G/400G and 800G high-performance computing SoCs for hyperscale data center, networking, and AI applications.
Comprehensive Portofolio of High-Speed SerDes PHYs
112G Ethernet PHY IP enables true long reach channels for up to 800G high-performance computing SoCs
56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications
Die-to-Die PHY IP enables ultra- and extra- short reach (USR/XSR) connectivity for up to 112G data rates
Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols
Educational Content Covering a Wide Range of Topics to Keep You Up-to-Date
Webinar: Keeping Latency to a Minimum with 400G/800G Ethernet IP
Webinar: Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution
Webinar: Ensuring Known Good Dies in SiPs with Die-to-Die PHY IP,
Webinar: The New Frontier of Die-to-Die Interface IP
Webinar: Leveraging IP to Enable Reliable Die-to-Die Connectivity
Whitepaper: Jitter Budgeting for Clock Distribution Networks in High-Speed PHYs and SerDes
Now Showing: Successful 112G PAM-4 System Interoperability Between Synopsys IP and Samtec Channel
DesignCon 2021 112G Ethernet & PCIe 6.0 IP Demos
DesignWare 112G Ethernet PHY IP JTOL & ITOL Performance
DesignWare 112G Ethernet PHY IP Insertion Loss Capabilities
Stay Current with the Latest News on High-Speed SerDes PHY IP
Synopsys IP Achieves Broad Industry Adoption on TSMC's N5 Process
Synopsys Completes Acquisition of MoreThanIP
Silicon-Proof of 112G Ethernet PHY IP in 5nm Process
IP for GF 12LP+ Targeting Cloud Computing and Edge AI SoCs
Chelsio Adopts DesignWare 56G Ethernet PHY IP for HPC Design
High-Performance Computing IP for TSMC's 5nm Process
Inomize Selects Synopsys' Silicon-Proven 56G Ethernet PHY IP
Additional Resources
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