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High-Speed SerDes IP Solutions

Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.

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Products +

<p><a href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_112g_ethernet_phy">112G Ethernet PH<span style="font-family: inherit;">Y IP</span></a><span style="font-family: inherit;"> enables true long reach channels for up to 800G high-performance computing SoCs</span></p><p><span style="font-family: inherit;"><a href="https://www.synopsys.com/dw/ipdir.php?ds=dwc_56g_ethernet_phy">56G Ethernet PHY IP</a> addresses reach and performance of up to 400G Ethernet applications</span></p><p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/die-to-die.html">Die-to-Die PHY IP</a> enables up to 112G XSR connectivity</span></p><p><span style="font-family: inherit;"><a href="/content/synopsys/en-us/designware-ip/interface-ip/multiprotocol-phys.html">Multi-Protocol PHYs</a> supports Ethernet, PCI Express, CCIX, CXL and more protocols</span></p><p><a href="/content/synopsys/en-us/designware-ip/interface-ip/pci-express.html">PCI Express PHY IP</a> enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes</p>

Comprehensive Portfolio

224G Ethernet PHY IP and 112G Ethernet PHY IP enable true long reach channels for up to 800G/1.6T high-performance computing SoCs

56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications

Die-to-Die PHY IP for UCIe and 112G XSR

Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols

PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes

Webinars & Whitepapers +

<p>Webinar: <a href="https://www.synopsys.com/designware-ip/resources/webinars/overcoming-pcie6-integration-and-validation-challenges.html?cmp=disp_ip_misc_07_14_22_1549306_wbr_ww_pcie_hhs20">Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges</a></p><p>Webinar: <a href="https://attendee.gotowebinar.com/register/1388436214572543504?source=Synopsys">PCIe 6.0 From IP to Interconnect in High-Performance Computing</a></p><p>Webinar: <a href="/content/synopsys/en-us/designware-ip/resources/webinars/minimize-latency-with-400g-800g-ethernet-ip.html">Keeping Latency to a Minimum with 400G/800G Ethernet IP</a></p><p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1474205&tp_key=82f85b7d37&sti=web">Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution</a></p><p>Webinar: <a href="https://readytalk.webcasts.com/starthere.jsp?ei=1466672&amp;tp_key=bc58fabe78&amp;sti=search">PCI Express 6.0 Design Considerations & IP Implementation</a></p><p>Whitepaper: <a href="https://www.synopsys.com/dw/doc.php/wp/Evolution_of_Data_Center_Networking_Technology-IP_and_Beyond_wp.pdf">Evolution of Data Center Networking Technology — IP and Beyond</a></p>

Educational Content Covering a Wide Range of Topics to Keep You Up-to-Date

Webinar: The Path to 1.6TbE with 224G Ethernet PHY IP

Webinar: Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

Webinar: PCIe 6.0 From IP to Interconnect in High-Performance Computing

Webinar: Keeping Latency to a Minimum with 400G/800G Ethernet IP

Webinar: Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution

Webinar: PCI Express 6.0 Design Considerations & IP Implementation

Videos +

Synopsys 224G, 112G Ethernet PHY IP and PCIe 6.0 IP at DesignCon 2023

First CXL 2.0 IP Interoperability Demo with Compliance Tests

Synopsys 224G & 112G Ethernet PHY IP OIF Interop at ECOC 2022

Synopsys 112G Ethernet PHY IP on TSMC N5 Performance Results

PCIe 6.0 End-to-End Hardware Linkup and Performance

Synopsys 112G Multi-Protocol PHY IP and Amphenol 2m DAC & Examax Interoperability

Latest News +

getty 546824255, servers, data center, network

Stay Current with the Latest News on High-Speed SerDes IP

Synopsys Accelerates First-Pass Silicon Success for Banias Labs' Networking SoC

Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process

100G Ethernet IP for Edge Computing

Reduce Integration Risks for High-Speed Applications with PCIe 5.0-Compliant Synopsys IP

Synopsys IP Achieves Broad Industry Adoption on TSMC's N5 Process

Synopsys Completes Acquisition of MoreThanIP

Podcasts +

iStock 500703366, audio, sound, sound wave, recording

Stay Current with the Latest Podcasts on High-Speed SerDes IP

800Gs Finally Breaking out and Benefits of Solution

The Impact of UCIe on Multi-Die Systems

Application Challenges to get to 1.6T using 224G Ethernet

How an ASIC Model for IP Can Accelerate Semiconductor Innovation

The Role of Synopsys High-Speed SerDes for Future Ethernet Applications

An All Inclusive Journey to HPC/Data Center Silicon Success

Featured Resources

Podcast

The Role of Synopsys High-Speed SerDes for Future Ethernet Applications

Blog

How Does Short-Reach Connectivity Transcend Physical and Power Limits?

Blog

A Primer on Chip Packaging for Multi-Die Designs

Article

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications

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