Cloud native EDA tools & pre-optimized hardware platforms
Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.
224G Ethernet PHY IP and 112G Ethernet PHY IP enable true long reach channels for up to 800G/1.6T high-performance computing SoCs
56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications
Die-to-Die PHY IP for UCIe and 112G XSR
Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols
PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes
Webinar: PCIe 6.0 Simulation and Electrical Testing for High Data-Bandwidth Applications
Webinar: How 100G 200G Electro-Optical Interfaces Enable Low Power, Low Latency Datacenters
Webinar: Key MAC Considerations for the Road to 1.6T Ethernet Success
Whitepaper: ESD Co-Design for High-Speed SerDes in FinFET Technologies
Synopsys 224G Ethernet PHY IP at TSMC Symposium
Synopsys and OpenLight Electro-Optical Link Demo
Synopsys 224G, 112G Ethernet PHY IP and PCIe 6.0 IP at DesignCon 2023
Synopsys 224G and 112G Ethernet PHY IP Demonstrations at OIF & OFC 2023
First CXL 2.0 IP Interoperability Demo with Compliance Tests
Synopsys 112G Ethernet PHY IP on TSMC N5 Performance Results
PCIe 6.0 End-to-End Hardware Linkup and Performance
How Are the Standards for the Terabit Era Defined?
800Gs Finally Breaking out and Benefits of Solution
The Impact of UCIe on Multi-Die Systems
Application Challenges to get to 1.6T using 224G Ethernet
How an ASIC Model for IP Can Accelerate Semiconductor Innovation
The Role of Synopsys High-Speed SerDes for Future Ethernet Applications