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DesignWare IP for PCI Express (PCIe) 6.0
Overview
Synopsys’ DesignWare IP for PCI Express (PCIe) 6.0 complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and IDE security module IP.
Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys’ DesignWare IP complete solution for PCI Express (PCIe) 6.0 is optimized to support the latest PCIe 6.0 specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.0 designs.
Accelerating PCIe 6.0 Designs with DesignWare IP
This video details how designers can make a successful shift to PCIe 6.0 technology, meeting latency, power and performance requirements for a range of applications including storage, retimers and AI accelerators.
DesignWare Controller and PHY IP for PCIe 6.0
See a demo of Synopsys’ complete IP solution for PCIe 6.0 technology showing the controller operating at 64GT/s in FLIT mode and the PAM-4 PHY in 5-nm process achieving two orders of magnitude better BER with 32dB PCIe channel.
DesignCon 2021 112G Ethernet & PCIe 6.0 IP Demos
This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.
Successful PCI Express 6.0 Designs at 64GT/s with IP
How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs
