Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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Synopsys IP for PCI Express (PCIe) 6.x complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and Integrity and Data Encryption (IDE) security module IP.
Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys IP complete solution for PCI Express (PCIe) 6.x is optimized to support the latest PCIe 6.x specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.x designs.
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What's New
Webinar
To Retime or Not to Retime? Getting Ready for PCIe and Ethernet over Linear Pluggable Optics
Video
World’s First PCIe 6.x Interop with Intel’s PCIe 6.0 Test Chip at Intel Innovation 2023
News Release
Synopsys Announces Industry's First Ultra Ethernet and UALink IP Solutions to Connect Massive AI Accelerator Clusters
Video
World's Most Interoperable PCIe 6.x and Beyond at PCI-SIG DevCon 2023
Video
Synopsys PCIe 6.x End-to-End Link Traffic Analysis at PCI-SIG DevCon 2023
