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DesignWare IP for PCI Express (PCIe) 6.0
Overview
Synopsys’ DesignWare IP for PCI Express (PCIe) 6.0 complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and IDE security module IP.
Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys’ DesignWare IP complete solution for PCI Express (PCIe) 6.0 is optimized to support the latest PCIe 6.0 specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.0 designs.
PCIe/CXL Latency and Power Considerations for HPC SoCs
How the Doubling of Interconnect Bandwidth with PCI Express® 6.0 Impacts IP Electrical Validation
PCIe 6.0 End-to-End Hardware Linkup and Performance
This PCI-SIG DevCon 2022 video shows the industry’s first complete hardware demo of PCIe 6.0 with an end-to-end system from root complex to endpoint. The demo uses the Synopsys PCIe 6.0 Controller and PHY IP and shows successful link up and performance metrics.
PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications
Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges
PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems.
PODCASTS