DesignWare IP for PCI Express (PCIe) 6.0


Synopsys’ DesignWare IP for PCI Express (PCIe) 6.0 complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and IDE security module IP.

Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys’ DesignWare IP complete solution for PCI Express (PCIe) 6.0 is optimized to support the latest PCIe 6.0 specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.0 designs. 

Data center

Data-Driven World Gets a Lift with First Two-Party PCIe v6.0 Linkup by Synopsys and Keysight

Data center

PCIe/CXL Latency and Power Considerations for HPC SoCs

chip, chips, semiconductor, semi, silicon, chip design, circuit

How the Doubling of Interconnect Bandwidth with PCI Express® 6.0 Impacts IP Electrical Validation

PCIe 6.0 End-to-End Hardware Linkup and Performance

This PCI-SIG DevCon 2022 video shows the industry’s first complete hardware demo of PCIe 6.0 with an end-to-end system from root complex to endpoint. The demo uses the Synopsys PCIe 6.0 Controller and PHY IP and shows successful link up and performance metrics.

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications