PCI Express (PCIe) 6.0 IP | DesignWare IP | Synopsys

DesignWare IP for PCI Express (PCIe) 6.0

Overview

Synopsys’ DesignWare IP for PCI Express (PCIe) 6.0 complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and IDE security module IP.

Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys’ DesignWare IP complete solution for PCI Express (PCIe) 6.0 is optimized to support the latest PCIe 6.0 specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.0 designs. 

PCIe 6.0 End-to-End Hardware Linkup and Performance

This PCI-SIG DevCon 2022 video shows the industry’s first complete hardware demo of PCIe 6.0 with an end-to-end system from root complex to endpoint. The demo uses the Synopsys PCIe 6.0 Controller and PHY IP and shows successful link up and performance metrics.

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications

<p>PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems.</p>

Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems.

Synopsys PCIe 6.0 IP TX and RX Successful Interoperability with Keysight

This DesignCon 2022 video features Synopsys PHY IP for PCIe 6.0 showing wide open PAM-4 eyes, good jitter breakdown decomposition on the Keysight oscilloscope, excellent receiver performance, and simulation-to-silicon correlation.

Accelerating PCIe 6.0 Designs with DesignWare IP

This video details how designers can make a successful shift to PCIe 6.0 technology, meeting latency, power and performance requirements for a range of applications including storage, retimers and AI accelerators.

DesignWare Controller and PHY IP for PCIe 6.0

See a demo of Synopsys’ complete IP solution for PCIe 6.0 technology showing the controller operating at 64GT/s in FLIT mode and the PAM-4 PHY in 5-nm process achieving two orders of magnitude better BER with 32dB PCIe channel.