Synopsys Controller IP for PCI Express 6.0

The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 6.0 supports all required features of the PCI Express 6.0 specifications, and can be configured by the user to support Endpoint (EP), Root Port, Dual Mode (DM), or Switch Port (SW) applications. The low-latency controller with new MultiStream architecture allows a full 64GT/s x16 lane bandwidth with support for up to 1024-bit data paths, while enabling timing closure at 1GHz. The controller can ensure optimal flow with multiple sources and in multivirtual channel implementations. Support for host, device, and dual mode enables early interoperability in absence of available 6.0 hosts and interop partners. Designers can achieve maximum throughput for Arm-based SoCs with the controller’s support for the Arm AXI and for advanced host features including deferrable memory writes. The controller's reliability, availability and serviceability (RAS) features enhance data integrity, simplify firmware development and improve link bring-up.

The Synopsys Integrity and Data Encryption (IDE) Security Module for PCIe 6.0 is pre-verified with the Synopsys Controller IP to help designers protect data transfer in their SoCs against tampering and physical attacks. The standards-compliant IDE Security Modules are designed and validated with Synopsys Controller IP for PCIe to accelerate SoC integration, offering efficient confidentiality, integrity, and replay protection.

Synopsys Controller IP for PCIe 6.0 seamlessly interoperates with the silicon-proven PHY IP for PCIe 6.0 in advanced FinFET processes to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology.

Synopsys Controller IP for PCI Express 6.0

 

Highlights
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Downloads and Documentation
  • Supports all required features of the PCI Express 6.0 (64 GT/s) specification
  • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
  • Supports advanced RAS data protection features including ECC
  • Supports the Synopsys native interface or the optional Arm® AMBA® 5/4/3 AXI application interface
  • Configurable for low power, small area and low latency
  • Enables efficient embedded DMA applications with Synopsys HyperDMA™
  • Optional support for PCI Express Link Encryption via Integrity and Data Encryption (IDE) ECN
  • Standards-compliant IDE Security Module protects data transfer for SoCs using the PCIe 6.0 interface
Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)STARs Subscribe
PCIe 6.0 (Gen6) Premium ControllerSTARs Subscribe
PCIe 6.0 (Gen6) Premium Controller with AMBA bridgeSTARs Subscribe
PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI InterfacesSTARs Subscribe

Description: Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
Name: dwc_pcie6_security_interface_add_on
Version: 6.10a-lca01
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dw_iip_DWC_pcie_ctl_gen6
Product Code: G169-0
  
Description: PCIe 6.0 (Gen6) Premium Controller
Name: dwc_pci_express_gen6_prem
Version: 6.10a-lca01
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dw_iip_DWC_pcie_ctl_gen6
Product Code: G166-0
  
Description: PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
Name: dwc_pci_express_gen6_prem_amba
Version: 6.10a-lca01
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dw_iip_DWC_pcie_ctl_gen6
Product Code: G167-0
  
Description: PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
Name: dwc_pci_express_gen6_prem_amba_hpc
ECCN:
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: