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DesignWare PCI Express (PCIe) IP Solutions
Overview
Synopsys’ DesignWare® IP Solutions for PCI Express® (PCIe®) consist of digital controllers, PHYs, IDE Security Modules, and verification IP. The IP solutions are designed to support all required features of the PCIe 6.0 64GT/s (Gen6), PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1), and latest PIPE specifications.
As the leading supplier of PCIe IP, Synopsys offers silicon-proven DesignWare IP solutions for PCIe that provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, AI, and automotive applications. Extensive interoperability testing with third-party products and strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk.
Products
Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges
PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems.
Synopsys PCIe 6.0 IP TX and RX Successful Interoperability with Keysight
This DesignCon 2022 video features Synopsys PHY IP for PCIe 6.0 showing wide open PAM-4 eyes, good jitter breakdown decomposition on the Keysight oscilloscope, excellent receiver performance, and simulation-to-silicon correlation.
Synopsys IP Passes PCIe 5.0 Compliance & Makes Integrators List
As the leading supplier of IP solutions for PCIe, Synopsys IP solutions for PCIe 5.0, including digital controllers and PHYs, have officially passed PCI-SIG 5.0 Compliance Testing and are the first IP to be listed on the 5.0 Integrators List.
What’s New in PCIe 6.0—Beyond the Bandwidth
Every successive generation of PCIe has doubled the bandwidth of the previous generation. PCIe 6.0 is no different. But in addition to increasing bandwidth, it’s the most significant PCI Express protocol innovation to date. Here is what you need to know.
5-nm DesignWare Multi-Protocol 112G PHY IP Long-Reach Demonstration
This video demonstrates the long reach performance of Synopsys' N5 multi-protocol 112G PHY IP transmitter and receiver, showing wide open PAM-4 eyes, maximum performance per lane, and post-FEC zero BER.
Accelerating PCIe 6.0 Designs with DesignWare IP
This video details how designers can make a successful shift to PCIe 6.0 technology, meeting latency, power and performance requirements for a range of applications including storage, retimers and AI accelerators.