DesignWare IP Solutions for PCI Express

Overview

Synopsys’ complete, silicon-proven DesignWare® IP for PCI Express® (PCIe®) solution includes a suite of digital controllers, PHYs, and verification IP, all of which are designed to the PCIe 4.0, 3.1, 2.1 and 1.1 (Gen4, Gen3, Gen2, Gen1) and PIPE specifications. In addition, Synopsys supports the M-PCIe™ ECN with silicon-proven M-PHY and M-PCIe Controller IP. As the leading supplier of PCIe IP, Synopsys’ DesignWare IP for PCIe® has gone through extensive third-party interoperability testing with products shipping in volume production. The strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk for next-generation mobile, consumer, communication, enterprise, IoT and automotive system-on-chips (SoCs). 

Highlights

Controller IP

  • Broad portfolio including Endpoint, Dual Mode, Root Port, and Switch/Bridge
  • Silicon proven; low latency and low gate count
  • Powers the Agilent and PCI-SIG protocol test card
  • Largest installed base of all PCI Express IP providers

PHY IP

  • Designed for integration of both upstream and downstream applications as well as PCI Express bridges and switches
  • Fully compliant with the PCI Express 3.x (8 GT/s), 2.x (5.0 GT/s), and 1.x (2.5 GT/s) as well as the PHY interface for PCIe 3.x (PIPE4 draft 6) (8-bit, 16-bit and 32-bit) specifications
  • Multi-tap adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
  • Extremely low in power consumption and size for smaller die area, improved jitter and sensitivity

Verification IP

  • Verifies all topologies of the controller including PCI Express endpoints, switches and root complex devices
  • Accelerates test development with built-in error injection and scoreboarding
  • Supports directed and constrained random traffic generation
  • Provides functional coverage of PCI Express transactions and coverage of the PCI Express compliance checklist
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