DesignWare IP Prototyping Kits for PCI Express 5.0, 4.0, 3.0 and CXL 2.0
The Synopsys IP Prototyping Kits for PCI Express 5.0, PCI Express 4.0 and PCI Express 3.0 center around a complete, out-of-the-box reference designs that consists of a validated PCIe and CXL Controller IP configurations and necessary SoC integration logic, implemented on Synopsys' HAPS® FPGA-based prototyping system. IP Prototyping Kits are available as soft deliverables requiring additional hardware prerequisites such as a HAPS system, cables, and other accessories. All IP kits include reference drivers, SoC integration logic, and application examples.
Synopsys IP Prototyping Kits for PCI Express 3.0 Controller Synopsys IP Prototyping Kits for PCI Express 4.0 Controller
|
|
Highlights
Products
Downloads and Documentation
- Supports Synopsys PCI Express 5.0, 4.0, 3.0 and CXL 2.0 Controllers
- Power management, clock and reset control block
- Pre-instrumented debug for most interfaces
- IP Prototyping Kits for PCI Express and CXL are available in the following configurations:
- Soft IP Prototyping Kits for use with your in-house HAPS system
- PCI Express 5.0 Endpoint
- PCI Express 5.0 Root Complex
- PCI Express 4.0 Endpoint
- PCI Express 4.0 Root Complex
- PCI Express 3.0 Endpoint
- PCI Express 3.0 Root Complex
- CXL 2.0 Gen3x4 Device
- CXL 2.0 Gen3x4 Host
| Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4,8 End Point on HAPS-100, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4,8 Root Port on HAPS-100, AXI tunnel to ARC HS | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4 End Point on HAPS-100, Xilinx GTY PHY, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4,8 Root Port on HAPS-100, Xilinx GTY PHY, AXI tunnel to ARC HS | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen4 x1,2,4 End Point on HAPS-100, Xilinx GTY PHY, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen4 x1,2,4 Root Port on HAPS-100, Xilinx GTY PHY, AXI tunnel to ARC HS | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 End Point on HAPS-100, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 Root Port on HAPS-100, AXI tunnel to ARC SDP | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4 End Point on HAPS-80, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4 Root Port on HAPS-80, AXI tunnel to ARC HS | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4 End Point on HAPS-80, Xilinx GTH PHY, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4 Root Port on HAPS-80, Xilinx GTH PHY, AXI tunnel to ARC SDP | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen4x1 End Point on HAPS-80, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen4x1 Root Port on HAPS-80, AXI tunnel to ARC SDP | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 End Point on HAPS-80, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 Root Port on HAPS-80, AXI tunnel to ARC SDP | STARs | Subscribe |
| Description: | Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4 End Point on HAPS-80, PCIe connection for PC |
| Name: | dwcipk_80_cxlg3ep_xlnxphy_pcie |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | G033-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4 Root Port on HAPS-80, AXI tunnel to ARC HS |
| Name: | dwcipk_80_cxlg3rp_xlnxphy_arc |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | G034-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4,8 End Point on HAPS-100, PCIe connection for PC |
| Name: | dwcipk_100_cxlg3ep_xlnxphy_pcie |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H330-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for CXL 2.0 Gen3x4,8 Root Port on HAPS-100, AXI tunnel to ARC HS |
| Name: | dwcipk_100_cxlg3rp_xlnxphy_arc |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H331-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4 End Point on HAPS-100, Xilinx GTY PHY, PCIe connection for PC |
| Name: | dwcipk_100_pcie3ep_xlnxphy_pcie |
| Version: | 6.00a |
| ECCN: | 3D991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H076-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4 End Point on HAPS-80, Xilinx GTH PHY, PCIe connection for PC |
| Name: | dwcipk_80_pcie3ep_xlnxphy_pcie |
| Version: | 6.00a |
| ECCN: | EAR99/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | C046-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4 Root Port on HAPS-80, Xilinx GTH PHY, AXI tunnel to ARC SDP |
| Name: | dwcipk_80_pcie3rp_xlnxphy_arc |
| Version: | 6.00a |
| ECCN: | 3D991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | E027-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen3 x1,2,4,8 Root Port on HAPS-100, Xilinx GTY PHY, AXI tunnel to ARC HS |
| Name: | dwcipk_100_pcie3rp_xlnxphy_arc |
| Version: | 6.00a |
| ECCN: | 3D991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H077-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen4 x1,2,4 End Point on HAPS-100, Xilinx GTY PHY, PCIe connection for PC |
| Name: | dwcipk_100_pcie4ep_xlnxphy_pcie |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H348-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen4 x1,2,4 Root Port on HAPS-100, Xilinx GTY PHY, AXI tunnel to ARC HS |
| Name: | dwcipk_100_pcie4rp_xlnxphy_arc |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H349-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen4x1 End Point on HAPS-80, PCIe connection for PC |
| Name: | dwcipk_80_pcie4ep_16gphy_pcie |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | E825-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen4x1 Root Port on HAPS-80, AXI tunnel to ARC SDP |
| Name: | dwcipk_80_pcie4rp_16gphy_arc |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | E826-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 End Point on HAPS-100, PCIe connection for PC |
| Name: | dwcipk_100_pcie5ep_32gphy_pcie |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H350-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 End Point on HAPS-80, PCIe connection for PC |
| Name: | dwcipk_80_pcie5ep_32gphy_pcie |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | E827-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 Root Port on HAPS-100, AXI tunnel to ARC SDP |
| Name: | dwcipk_100_pcie5rp_32gphy_arc |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | H351-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for PCIe Gen5x1 Root Port on HAPS-80, AXI tunnel to ARC SDP |
| Name: | dwcipk_80_pcie5rp_32gphy_arc |
| Version: | 6.00a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_pcie |
| Product Code: | E828-0 |
Search Tools