DesignWare IP Prototyping Kits for PCI Express 4.0, 3.0 & 2.0

The DesignWare® IP Prototyping Kits for PCI Express 4.0, PCI Express 3.0 and PCI Express 2.0 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system.

With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. The prototyping kits take advantage of Synopsys’ HAPS Developer eXpress (HAPS-DX) system to provide prototyping hardware and software automation tools. Scripts and configuration files enable fast iteration.

The IP Prototyping Kits can be used as a physical target for early software bring-up, debug and test concurrently with SoC development. Out-of-the-box support for Linux software stack or Windows ensures that software developers are up and running instantly and can focus on the IP specific software (e.g., drivers, bootcode, firmware). The kits plugs into existing software tool chains and interfaces seamlessly with popular embedded software debuggers, providing system-wide debug and analysis capabilities.

DesignWare IP Prototyping Kit for PCIe 2.0 Endpoint Controller with PCIe Connection to PC and Optional ARC Software Development Platform
DesignWare IP Prototyping Kit for PCIe 3.0 Dual Mode Controller in Root Complex Mode with ARC Software Development Platform
DesignWare IP Prototyping Kit for PCIe 3.0 Endpoint Controller with PCIe Connection to PC and Optional ARC Software Development Platform
DesignWare IP Prototyping Kit for PCIe 4.0 Root Complex with ARC Software Development Platform

 

Highlights
Products
Downloads and Documentation
  • Multiple kit and configuration options available
    • DesignWare IP Prototyping Kit for PCI Express 3.0 Endpoint offers connectivity to PC and optional ARC Software Development Platform
    • DesignWare IP Prototyping Kit for PCI Express 3.0 Root Complex with ARC Software Development Platform
    • DesignWare IP Prototyping Kit for PCI Express 2.0 Endpoint offers connectivity to PC and optional ARC Software Development Platform
  • Power management, clock and reset control block
  • Pre-instrumented debug for most interfaces
IP Prototyping Kit Soft Deliverable for DWC PCIe Gen2x1 Dual Mode on HAPS-70, Xilinx GTX PHY, AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit Soft Deliverable for DWC PCIe Gen3x4 End Point on HAPS-80, Xilinx GTH PHY, PCIe connection for PCSTARs Subscribe
IP Prototyping Kit Soft Deliverable for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen2 x1,x2,x4 Endpoint Controller on HAPS-80, Xilinx GTH PHY, PCIe connection for PCSTARs Subscribe
IP Prototyping Kit for PCIe Gen2x1 Endpoint Controller on HAPS-DX7, Consumer 6 Gig PHY card, PCIe Connection for PCSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Endpoint Controller on HAPS-DX7, PCIe 3.0 PHY (C10), PCIe connection for PCSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Endpoint Controller on HAPS-DX7, PCIe 3.0 PHY (C8), PCIe connection for PCSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Endpoint Controller on HAPS-DX7, Xilinx GTH PHY, PCIe connection for PCSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex Controller on HAPS-DX7, PCIe 3.0 PHY (C10), AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, PCIe 3.0 PHY (C8), AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDPSTARs Subscribe

Description: IP Prototyping Kit for DWC PCIe Gen2 x1,x2,x4 Endpoint Controller on HAPS-80, Xilinx GTH PHY, PCIe connection for PC
Name: dwipk_pcie2ep_80xlnxphy_pcie
Version: 1.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe2-EP-XLNXPHY-PCIe
Product Code: HW0358-0
  
Description: IP Prototyping Kit for DWC PCIe Gen3x1 Endpoint Controller on HAPS-DX7, PCIe 3.0 PHY (C10), PCIe connection for PC
Name: dwipk_pcie3ep_10gphy_pcie
Version: 1.01a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe3-EP-10G-PHY_PCIe
Product Code: HW0370-0
  
Description: IP Prototyping Kit for DWC PCIe Gen3x1 Endpoint Controller on HAPS-DX7, PCIe 3.0 PHY (C8), PCIe connection for PC
Name: dwipk_pcie3ep_8gphy_pcie
Version: 1.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe3-EP-8G-PHY_PCIe
Product Code: HW0386-0
  
Description: IP Prototyping Kit for DWC PCIe Gen3x1 Endpoint Controller on HAPS-DX7, Xilinx GTH PHY, PCIe connection for PC
Name: dwipk_pcie3ep_xlnxphy_pcie
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe-3-EP-XLNXPHY_PCIe
Product Code: HW0285-0
  
Description: IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex Controller on HAPS-DX7, PCIe 3.0 PHY (C10), AXI tunnel to ARC SDP
Name: dwipk_pcie3rc_10gphy_arc
Version: 1.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe3-RC-10G-PHY_ARC
Product Code: HW0371-0
  
Description: IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, PCIe 3.0 PHY (C8), AXI tunnel to ARC SDP
Name: dwipk_pcie3rc_8gphy_arc
Version: 1.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe3-RC-8G-PHY_ARC
Product Code: HW0374-0
  
Description: IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDP
Name: dwipk_pcie3rc_xlnxphy_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe3-RC-XLNXPHY_ARC
Product Code: HW0297-0
  
Description: IP Prototyping Kit for PCIe Gen2x1 Endpoint Controller on HAPS-DX7, Consumer 6 Gig PHY card, PCIe Connection for PC
Name: dwipk_pcie2ep_c6gphy_pcie
Version: 2.20c
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe2-EP-6G-PHY_PCIe
Product Code: HW0296-0
  
Description: IP Prototyping Kit Soft Deliverable for DWC PCIe Gen2x1 Dual Mode on HAPS-70, Xilinx GTX PHY, AXI tunnel to ARC SDP
Name: dwcipk_pcie2dm_70xlnxphy_arc
Version: 1.10a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Product Code: B938-0
  
Description: IP Prototyping Kit Soft Deliverable for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDP
Name: dwcipk_pcie3rc_xlnxphy_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_PCIe3-RC-XLNXPHY_ARC
Product Code: C337-0
  
Description: IP Prototyping Kit Soft Deliverable for DWC PCIe Gen3x4 End Point on HAPS-80, Xilinx GTH PHY, PCIe connection for PC
Name: dwcipk_pcie3ep_80xlnxphy_pcie
Version: 1.00c
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_80-PCIe3-EP-XLNXPHY-PCIe
Product Code: C046-0