DesignWare IP for PCI Express 4.0

Overview

Synopsys’ complete DesignWare IP solution for PCI Express (PCIe) 4.0 operating at 16GT/s data rates enables real-time data connectivity with low-latency and high-performance for automotive, mobile, cloud computing, networking, and storage SoCs.

The low-power, compact IP is the industry’s first, most thoroughly tested and interoperated solution available for PCIe 4.0. Used in all the pre-FYI and FYI compliance testing, and now with multiple entries on the official PCI-SIG Integrators List for both PHY and controller, Synopsys offers the lowest risk solution supporting the key features of the PCIe 4.0 and PIPE specifications. Synopsys, the industry’s leading IP provider for PCIe, is an active member of the PCI-SIG standards organization, actively contributing to the development and adoption of the PCIe specification. overall, the DesignWare IP for PCI Express has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market.

Controller IP for PCI Express 4.0

The silicon-proven controller IP for PCIe 4.0 offers flexible datapath support from 32-bit to 512-bit, with lane widths ranging from x1 to x16, providing maximum throughput required for data intensive applications. Synopsys' PCIe 4.0 controller offers industry’s first production-proven 512-bit architecture, providing flexible options to optimize latency and timing closure for SoCs. For best latency performance, the Synopsys controller has demonstrated 1GHz timing closure in real customer applications. The controller IP can be user-configured to support Dual Mode, Endpoint, Root Port, and Switch applications in your choice of datapath widths, PIPE interface widths, and operating frequencies, helping to optimize for size, power, latency, and throughput. The controller also includes a rich feature set with extensive ECN support. Advanced RAS features including data protection, extensive debug capabilities, error injection and statistical monitoring helps designers successfully debug and resolve PCI Express linkup issues.

PHY IP for PCI Express 4.0

The PHY IP with leading power, performance, and area is available in a range of advanced FinFET process nodes for a wide range of foundries. Delivering exceptional signal integrity and jitter performance that exceeds the PCIe standards electrical specifications, the PHY meets the needs of high-speed chip-to-chip, board-to-board, and backplane interfaces. In addition, Synopsys’ PHY IP for PCIe 4.0 supports up to 25GT/s data rates for CCIX and medium reach Ethernet. 

Verification IP for PCI Express 4.0

Synopsys VC Verification IP (VIP) for the PCI Express provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of PCIe 4.0 designs. It accelerates testbench development, providing easy-to-use APIs for generating PCIe traffic.