PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers to their use in consumer electronics. PCI Express links carry high value information between the host and the peripheral and from endpoint to endpoint.
The Synopsys DesignWare® Integrity and Data Encryption (IDE) Security IP Module for PCIe 5.0 provides confidentiality, integrity, and replay protection for Transaction Layer Packets (TLP) over PCI Express interfaces as defined in the PCI-SIG IDE specification. The security module integrates seamlessly with the DesignWare PCIe 5.0 controllers to accelerate SoC integration.
The DesignWare IDE Security Module for PCIe 5.0 offers seamless integration with the DesignWare Controller for PCIe 5.0 via a TLP packet-based interface. The packet-based interface matches the data width used by the controller, e.g., 512-bit or 256-bit, together with the maximum number of TLP prefixes to offer an optimal performance vs. area implementation.
The IDE extended capability registers are accessible from the DesignWare Controller for PCIe 5.0, offering a clear view of the link capabilities during discovery and configuration timeframes.
Interoperability between the DesignWare IDE Security Module and Controller for PCIe 5.0 is part of the development process, offering customers version compatibility and reference integration templates
DesignWare IDE Security IP Module for PCI Express 5.0
Downloads and Documentation
- Compliant with PCI Express IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys controllers via TLP packet-based interface
- Support for PCIe 5.0, 4.0 and 3.0 data rates
- Customer configurable
- Aligns with PCIe controller’s configuration options
- Scalable data bus width: 128, 256, 512
- Lanes: x1, x2, x4, x8, x16
- Optimized for area, performance & latency
- Multi-stream support
- PCRC calculation & validation
- Efficient key control & refresh