The intent with the new PCIe 5.0 specification is to minimalize the changes to enable the specification to proceed quickly through the specification process. In fact, the schedule being driven into the working groups is very aggressive, especially if you compare to what we seen for the releases of the PCIe 4.0 specification. The initial 0.3 version of the PCIe 5.0 specification confirms the intent for minimal changes in features, so most of the work to update the controller will be to support the double data rates.
Synopsys has a long history of providing several PCIe IP “firsts” enabling our customers to develop SoCs with the latest (and I’d say best) PCIe interfaces to meet their aggressive rollouts while utilizing the latest PCIe technology. Beginning with the first day of the conference, on June 7, 2017, Synopsys was showcasing our support for PCIe 5.0 in our booth. In case you were not able to come to the show, you can see the video that we recorded of the First Demonstration of PCI Express 5.0 at 32GT/s.