Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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Unleash Maximum Throughput
Hyperscale data centers need access to ultra-efficient interfaces to support multi-trillion parameter AI compute models. Synopsys’ UALink IP solution offers maximum throughput per lane at 200 Gbps, providing the performance needed to scale-up to 1,024 AI accelerator links. Consisting of controller, PHY, and verification IP, the complete UALink IP solution is engineered for data-intensive AI workloads offering low latency, high bandwidth, and advanced memory sharing capabilities. Built on decades of design experience in high-speed PCIe and Ethernet IP, Synopsys’ UALink IP reduces integration risk and speeds time to market for AI and HPC chip designers unleashing next-gen AI infrastructures.
Key Benefits
Features
- Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
- Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
- Enables maximum throughput with up to 200Gbps per lane
- Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
- Supports high density, high radix networking infrastructure for AI workloads
- Enables full hardware security needs for UALink specifications
What's New
Related Products and Solutions
Synopsys provides the industry’s broadest IP portfolio for HPC and AI, enabling designers with best-in-class IP interfaces so designers can speed time to market and achieve first pass silicon success.
- Complete PCI Express 7.0 IP Solution
- Ultra Ethernet IP Solution
- Complete 1.6T Ethernet IP Solution
Resources
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Synopsys 224G IP Solution Shows Widest Multi-Vendor Interop at ECOC 2024
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Synopsys 800G MAC, PCS and PHY IP Interop with Switches and Optical Links at ECOC 2024
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Synopsys 224G IP Shows Ecosystem Interops for 1.6Tbps AI Networks at DesignCon 2025
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