Securing UALink: Introducing Synopsys UALinkSec_200 Security Module

Dana Neustadter, Vincent van der Leest

Jan 15, 2026 / 5 min read

Over the next decade, artificial intelligence will dominate computing, driving profound changes in both hardware and software architectures. This transformation will reshape data center design and interconnect technologies, creating new opportunities for innovation. As AI workloads scale, the need for high-speed, low-latency communication between accelerators becomes critical.

UALink is emerging as a crucial interface within this ecosystem, specifically designed to enhance the scalability of AI networks. It is a next-generation interconnect protocol designed specifically for AI workloads and accelerator scale-up within a rack. Introduced in late 2024, with version 1.0 released in April 2025, UALink delivers a lightweight, low-latency, and high-speed architecture that evolves with market needs. Next to certain proprietary solutions that are currently available in the market, UALink aims to establish a standardized ecosystem, enabling interoperability and accelerating adoption across the industry.

The Importance of Security for UALink

Initially, security was considered outside the scope of the UALink specification, with the assumption that higher layers would address it. However, as the protocol matured, the need for integrated security became clear. Starting with version 0.7 and evolving through version 0.97, UALink introduced UALinkSec, a dedicated security framework for point-to-point accelerator links. The drivers behind this need for security include the expanding volumes of sensitive data being transported, growing regulatory requirements, and the rapid adoption of AI in critical applications. 

To protect the data traveling across UALink, implementing strong encryption and authentication mechanisms is essential. Encryption serves as a mandatory measure to maintain data confidentiality, ensuring that sensitive information remains inaccessible to unauthorized entities. Meanwhile, authentication, although optional, plays a critical role in enhancing the security framework. It verifies the integrity and origin of the data, providing an additional layer of protection. These security measures are not just technical necessities; they are vital strategies to prevent data from being intercepted or tampered with during its journey across the network. Without these safeguards, data centers risk exposure to breaches that could compromise AI models, intellectual property, and customer data.

Synopsys Launches Industry’s First Complete Secure UALink Solution

Synopsys has played a leading role in the evolution of the security standard for this interface as part the UALink consortium’s board of directors. Now the company proudly unveils the Synopsys UALinkSec_200 Security Module, setting a new benchmark as the first and most comprehensive security module IP available in the market. This innovative product is a testament to the company’s extensive expertise in securing advanced HPC interconnects, which has been leveraged to address the specific security needs of the UALink interface. 

The UALinkSec_200 Security Module aligns with the UALinkSec component from the UALink 200 v1.0 specification and is engineered to provide highly efficient encryption and decryption capabilities, utilizing the AES-GCM cryptographic algorithm. Additionally, it offers key derivation functionality and optional authentication support, allowing for flexible security configurations tailored to specific requirements and thus ensuring that data remains secure throughout its entire journey, from transmission to reception.

Figure 1. High-level architecture of the Synopsys UALinkSec_200 Security Module

The UALinkSec_200 Security Module embodies a holistic approach to data security. By integrating advanced security features, it offers a robust framework that protects against unauthorized access and potential data breaches. The solution is designed to seamlessly integrate with existing Synopsys UALink controllers, offering plug-and-play compatibility that simplifies deployment and reduces integration time. With support for high-speed data transfer of up to 200 GT/s per lane, enabled by the silicon-proven Synopsys 224G PHY IP, the UALinkSec_200 Security Module ensures that performance is not compromised for security.

Moreover, the UALinkSec_200 Security Module is equipped with features that cater to flexible configurations, supporting bifurcation for up to four ports and accommodating up to 1024 accelerators in the system. This flexibility is crucial for adapting to the diverse needs of modern data centers, allowing for tailored security configurations that meet specific requirements. The inclusion of failsafe operations, such as key rotation, freshness monitoring, and on-the-fly key derivation, further enhances the security posture by ensuring data protection even when keys are not programmed.


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Product Highlights and Features

  • Plug-and-Play Compatibility: Seamlessly integrates with Synopsys UALink controllers.
  • High-Speed Support: Accommodates up to 200 GT/s per lane, enabled by silicon-proven Synopsys 224G PHY IP.
  • Advanced Security: Features low-latency encryption/decryption and authentication, optimized AES-GCM operations, and support for FIPS 140-3 security certification.
  • Flexible Configurations: Supports bifurcation for up to 4 ports and up to 1024 accelerators in the system.
  • Failsafe Operations: Includes key rotation, freshness monitoring, and on-the-fly key derivation to protect data when keys are not programmed.

Synopsys UALinkSec System Integration

One of the key advantages of the UALinkSec_200 Security Module is its tight integration with Synopsys’ UALink Controller and silicon-proven 224G PHY IP. This interoperability ensures that designers can implement security without introducing complexity or latency penalties. The module connects through a standardized UPLI interface, enabling plug-and-play functionality that accelerates design cycles and reduces integration risk.

Figure 2 illustrates the system-level integration of the Synopsys solution, encompassing the UALinkSec_200 Security Module, UALink Controller and PHY, as well as additional security components such as the tRoot HSM (Hardware Secure Module) and SRAM PUF (Physical Unclonable Function).

Figure 2. System-level integration of Synopsys UALinkSec_200 Security Module

In this specific implementation, the Synopsys PUF generates a unique cryptographic root key based on the physical characteristics of the device, ensuring that this key never needs to be stored but can be regenerated as needed. This root key serves as the foundation for deriving additional keys, including those used by the UALinkSec_200 Security Module for secure operations. Meanwhile, tRoot HSM is responsible for programming these derived keys into the UALinkSec_200 Security Module, ensuring that the necessary cryptographic keys are securely integrated into the system. 

The UALinkSec_200 Security Module works seamlessly with all these other Synopsys components to provide a robust security framework, facilitating secure data transmission and enhancing the overall integrity of the system.

Enhancing Security with UALinkSec

In the digital age, where data is a critical asset, ensuring its security as it traverses the UALink interfaces is of utmost importance. UALink is engineered specifically to address the unique needs of modern, scalable AI infrastructures, with the ability to support high-speed data transfer so data centers can maintain operational efficiency while safeguarding sensitive information.

The newly launched UALinkSec_200 Security Module from Synopsys delivers the required security solution for this interface, providing SoC designers with a standards-aligned approach that supports advanced features to ensure robust data confidentiality and integrity with optimal performance, latency, area, and power. Its flexible configuration options and seamless integration capabilities make it adaptable to the diverse needs of modern data centers, enabling tailored security solutions that meet the requirements of high-speed AI infrastructures.

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