Date: Oct 15, 2026 | 9:00 AM PST
Featured Speaker:
As AI/ML clusters scale toward 800G, 1.6T, and beyond, the optical DSP/retimer functions inside conventional transceivers (FRO) are becoming a significant bottleneck — adding power, latency, and cost to every link at a time when interconnects already account for roughly 27% of data center power usage. Linear optics take a different approach: removing the optical DSP/retimer from the transceiver and shifting the equalization function to the host SerDes, reducing module power by up to 50% while lowering latency and cost. The trade-off is that the host PHY must now carry the full burden of signal integrity, equalization, and data recovery across real-world channel conditions, while adhering to a common industry standard to ensure Multi-Source Agreement interoperability across vendors.
Join to see how the industry's first 112G PHY IP compliant with OIF-CEI-112G-LINEAR-PAM4 was validated in silicon, meeting — and in some cases exceeding — the spec's transmitter and receiver electrical requirements.
What You'll Learn: