CXL 4.0 Arrives — Synopsys Unlocks the Next Leap in AI-Scale Memory Connectivity

The bottleneck in modern AI infrastructure has shifted. It's no longer raw compute—it's memory.

Modern LLM inference is dominated not by matrix math, but by memory access. Key-value caches balloon with context length. Model weights consume hundreds of gigabytes. Expert routing and shared state stretch across racks. According to Goldman Sachs Research, global AI token consumption is projected to grow 24× by 2030—reaching ~120 quadrillion tokens per month, pushing memory bandwidth, capacity, and latency well past what conventional interconnects were designed to deliver.

Hyperscalers, chip designers, and system architects have been left to redesign the fabric between CPUs, XPUs, accelerators, and memory itself. Compute Express Link® (CXL)—the open, cache-coherent interconnect built on the PCIe physical layer—has become the standards-based answer.

CXL 4.0 arrives with the biggest generational leap the specification has seen. And Synopsys is announcing the industry's first complete CXL 4.0 IP solution—Controller, IDE Security Module, silicon-proven PHY, and Verification IP—to help design teams turn that leap into shipping silicon.

CXL 2.0 introduced pooling and IDE security and has successfully deployed system memory expansion. CXL 3.x added switching and fabric scale and is beginning to deploy memory pooling & security introduced in CXL 2.0. CXL 4.0 is where the fabric catches up to AI, supporting higher bandwidths enabling a complete disaggregated computing system.

The specification doubles system bandwidth to 128 GT/s—aligned to PCIe 7.0—with zero added latency over CXL 3.x. New Bundled Port capabilities can enable over 2TB/s bandwidths bundling 4 x16 links or over 4TB/s bandwidths bundling 8 x16 links. This outpaces industry leading proprietary link bandwidths per GPU. In addition, 4-retimer support and native x2 link widths extend fabric reach at rack scale.

For AI system architects, that changes the economics of inference in three concrete ways:

• KV cache offload accelerates 3–6× vs. SSD-based alternatives at 128 GT/s.
• CXL.mem load-to-use latency drops below 200 ns—near cache-coherent territory.
• Rack-scale memory pooling exceeds 100 TB, cutting inference cost by an estimated 50–100%

Every generational jump in an open standard puts pressure on the design teams building around it. CXL 4.0 is no exception, and three challenges consistently surface in AI SoC roadmaps:

• Multi-generation support for hardware bottlenecks: Next generation SoCs must support additional memory capabilities in terms of capacity, bandwidth, and availability to avoid bottlenecks. CXL 2.0, 3.x, and 4.0 offer a standards based solution with backwards compatibility and leverage the PCIe SerDes PHY unlocking infrastructure value and enabling flexibility for AI systems well beyond the value a proprietary system can provide as software and AI models continue to outpace hardware market adoption.
• Security without a latency penalty: Multi-tenant AI and cloud deployments demand encrypted, authenticated, root-of-trust-anchored coherent memory. Any measurable latency cost erodes the value of the interconnect.
• A shrinking time-to-silicon window: In the AI infrastructure cycle, a missed quarter is a missed hyperscaler design win.

Solving any one of these takes more than a controller. It takes a complete, co-verified, silicon-proven stack.

Synopsys CXL IP delivers that complete stack, supporting CXL 4.0, 3.x, 2.0, and 1.x on a single unified architecture:

• CXL Controller: Full CXL 4.0 at 128 GT/s with backward compatibility, Bundled Ports, Port-Based Routing, and 256B Latency-Optimized FLIT support. One license spans every CXL generation and includes PCIe 7.0 fallback—no separate PCIe 7.0 IP license required.
• IDE Security Modules: Highly efficient AES-GCM based encryption and authentication with zero-cycle latency overhead on CXL.cache/CXL.mem skid mode, TSP/TDISP support for confidential computing, FIPS 140-3 security certification ready.
• CXL PHY: Silicon-proven PCIe 7.0-based SerDes at 128 GT/s, hardened from 5nm through 2nm, with low JTOL and low-latency FEC.
• Verification IP: The industry's first commercial CXL 4.0 VIP, so compliance and interop don't become the critical path.

The result for design teams is straightforward: one IP solution, every CXL generation, first-pass silicon, secure by default—built on 25+ years of PCIe leadership, 3,800+ PCIe design wins, 170+ CXL controllers and PHYs shipped, and deep expertise in interoperability and compliance.

CXL 4.0 is one interface in a much larger picture. Building the next generation of AI SoCs takes a coordinated silicon foundation—and CXL 4.0 slots into Synopsys' broader HPC IP portfolio alongside:

• Interface IP: CXL, PCIe, UCIe, UALink, Ultra Ethernet, ESUN and 224G/448G Ethernet PHY for scale-up and scale-out fabrics.
• Foundation IP: Memory, logic libraries, and standard cells hardened at leading-edge nodes.
• Security IP: Root of trust, PUF, post quantum cryptography, security protocol accelerators and interface security including PCIe & CXL IDEs, IME, MACsec and UALinkSec
• IP Subsystems: Pre-integrated, pre-verified blocks that shorten XPU and hyperscaler SoC design cycles.

Together, they form the silicon platform behind the XPUs, accelerators, and data-fabric switches powering Agentic AI.

CXL 4.0 marks the point where cache-coherent interconnect finally moves at AI's pace—doubling bandwidth to 128 GT/s, extending memory pooling past 100 TB per rack, and cutting inference cost without adding latency. Getting there in silicon takes more than a specification. The complete Synopsys CXL 4.0 IP portfolio—Controller, IDE Security, PHY, and VIP—gives design teams a single, silicon-proven path across every CXL generation, backed by two-plus decades of PCIe leadership and the deepest CXL deployment track record in the industry.