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AI and HPC workloads are outpacing what traditional interconnects can deliver. Memory is stranded, bandwidth is capped, and inference cost keeps climbing. Compute Express Link® solves this by making memory coherent, poolable, and shareable securely across CPUs, XPUs, and accelerators — at rack scale.
Synopsys CXL IP gets you there faster with a complete, silicon-proven solution spanning CXL 4.0, 3.x, 2.0, and 1.x — backed by the industry's most proven PCIe foundation, with 25+ years of PCIe leadership and thousands of PCIe design wins behind every link.
What's New
Products
Key Benefits
Features
- Support for all CXL generations — 4.0, 3.x, 2.0, and 1.x — on a single, unified IP stack
- Silicon-proven PCIe-based PHY spanning 32G, 64G, and 128 GT/s — hardened from 5nm through 2nm
- All CXL device types, host, and switch — with runtime dual-mode selection
- Integrated IDE Security across CXL 2.0, 3.x and 4.0 — AES-GCM encryption, TSP/TDISP, FIPS 140-3 ready
- Industry's first commercial CXL 4.0 Verification IP, plus VIP coverage for prior generations
Resources
World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
Enabling the Next Generation of AI Infrastructure with Ethernet for Scale-Up Networking (ESUN)
Synopsys PCIe Leadership Recognized: Paul Cassidy Joins a Track Record of PCI-SIG Contribution
FAQ — Why CXL?
CXL is an open, cache-coherent interconnect built on PCIe. It lets CPUs, XPUs, and accelerators share memory with near-cache latency — the foundation for solving AI's memory wall.
CXL 4.0 doubles bandwidth to 128 GT/s and adds new Bundled Port capabilities can enable over 2TB/s bandwidths bundling 4 x16 links or over 4TB/s bandwidths bundling 8 x16 links.
CXL.mem enables rack-scale coherent memory pooling, accelerating KV cache offload 3–6× vs. SSD alternatives with sub-200 ns load-to-use latency.
Yes. CXL 4.0 includes IDE security, fabric protections, and enhanced RAS. Synopsys IDE Security Modules deliver AES-GCM based encryption and authentication with zero-cycle overhead for CXL .cache/.mem and TSP/TDISP for confidential computing/virtualization support.