Compute Express Link (CXL)

Synopsys VC VIP Subsystem for Compute Express Link (CXL) provides a comprehensive set of protocol and subsystem level, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CXL subsystems.

VIP for Subsystems for Compute Express Link


  • Native SystemVerilog/UVM
  • Source code test suite (Optional)
  • Complete subsystem verification solution
  • Built-in protocol checks
  • Verification plan and coverage
  • Verdi® Protocol Analyzer
  • Extensive error injection
  • Runs on all major simulators

Key Features

  • CXL block level, sub-system level, and chip level (full stack) topologies
  • CXL transport, normal PCIe traffic verification, no coherency verification
  • CXL memory and cache coherency verification (CXL.mem+CXL.cache)
  • Configurable as CXL mem/cache protocol layer only (or) both protocol and link layer
  • Interface towards TB
    • PCIe TLM
    • TLM
    • CXL Flit TLM
    • CXL Req/Data/Resp TLM
  • PCIe LPC/ PIPE SerDes architecture / Serial signaling interface
  • Callbacks, error injection, PCIe/ CXL functional coverage