Compute Express Link (CXL)

Synopsys VC VIP Subsystem for Compute Express Link (CXL) provides a comprehensive set of protocol and subsystem level, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CXL subsystems.

VIP for Subsystems for Compute Express Link


  • Native SystemVerilog/UVM
  • Source code test suite (Optional)
  • Complete subsystem verification solution
  • Built-in protocol checks
  • Runs on all major simulators

Key Features

  • CXL 2.0 (EA)/CXL 1.1
  • Device Support
    • Type 1 – + CXL.cache (Accelerators)CXL block level, sub-system level, and chip level (full stack) topologies
    • Type 2 – + CXL.mem + CXL. cache (Dense Computation devices)
    • Type 3 – +CXL.mem (Memory Expanders)
  • Standalone PCIe Feature Testing capable - Producer-Consumer
  • CXL memory and cache coherency Transaction support
  • Flit based Transactions at ARB MUX
  • Topology based connections
  • Block level / Subsystem level
    • PCIe TLMs at TL/DL
    • TLM
    • CXL Flit TLM – CXL Req/ Data/Resp TLM
    • Logical PHY Interface (LPIF) v 1.1
  • Full Stack
    • PCIe LPC/ PIPE SerDes architecture/ Serial
  • Analysis ports for Scoreboard Applications
  • Callbacks, error injection, PCIe/ CXL functional coverage
  • Extensive Waveform, Layered Trace File support