Synopsys VC VIP Subsystem for Compute Express Link (CXL) provides a comprehensive set of protocol and subsystem level, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CXL subsystems.
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Compute Express Link (CXL)
Highlights
- Native SystemVerilog/UVM
- Source code test suite (Optional)
- Complete subsystem verification solution
- Built-in protocol checks
- Runs on all major simulators
Key Features
- Device Support
- Type 1 – CXL.io + CXL.cache (Accelerators)CXL block level, sub-system level, and chip level (full stack) topologies
- Type 2 – CXL.io + CXL.mem + CXL. cache (Dense Computation devices)
- Type 3 – CXL.io +CXL.mem (Memory Expanders)
- Standalone PCIe Feature Testing capable - Producer-Consumer
- CXL memory and cache coherency Transaction support
- Flit based Transactions at ARB MUX
- Topology based connections
- Block level / Subsystem level
- PCIe TLMs at TL/DL
- CXL.io/mem/cache TLM
- CXL Flit TLM – CXL Req/ Data/Resp TLM
- Logical PHY Interface (LPIF) v 1.1
- Full Stack
- PCIe LPC/ PIPE SerDes architecture/ Serial
- Analysis ports for Scoreboard Applications
- Callbacks, error injection, PCIe/ CXL functional coverage
- Extensive Waveform, Layered Trace File support