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About Compute Express Link
Synopsys VC VIP Subsystem for Compute Express Link (CXL) provides a comprehensive set of protocol and subsystem level, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of CXL subsystems.
Key Benefits
Native SystemVerilog/UVM
Source Code Test Suites Available
Built-in
Protocol Checks
Complete Subsystem Verification Solution
Features
- Supports CXL 3.0(EA), CXL 2.0, CXL 1.1 specifications
- Device Support
- Type 1 – CXL.io + CXL.cache (Accelerators)CXL block level, sub-system level, and chip level (full stack) topologies
- Type 2 – CXL.io + CXL.mem + CXL. cache (Dense Computation devices)
- Type 3 – CXL.io +CXL.mem (Memory Expanders)
- Standalone PCIe feature testing capablility - Producer-Consumer
- CXL memory and cache coherency transaction support
- FLIT based transactions at ARB/MUX
- Topology based connections
- Block level/Subsystem level
- PCIe TLMs at TL/DL
- CXL.io/mem/cache TLM
- CXL FLIT TLM – CXL Req/ Data/Resp TLM
- Logical PHY Interface (LPIF) v 1.1
- Full Stack
- PCIe LPC/ PIPE SerDes architecture/Serial
- Analysis ports for scoreboard applications
- Callbacks, error injection, PCIe/ CXL functional coverage
- Extensive Waveform, Layered Trace File support
News and Blogs
Blog
News Release
Synopsys Announces Industry's First CXL 2.0 VIP Solution for Breakthrough SoC Performance
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Webinar
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