Verification IP for PCI Express up to Gen 7 (PCIe)

Specifications: PCIe Gen 7/6/5/4/3/2/1, Gen 7/6/5 IDE

Interfaces: PIPE up to 7.0, SERDES interface up to 32 lanes

DUT Types/Topology

• Endpoint (EP), Root Complex (RC), PHY, Retimer

Key VIP Features

• Full protocol stack: Application (Driver, Target, Requester), Transaction, Link, and Phy layers​
• Specification-linked protocol checks and functional coverage
• Scoreboard, callbacks and error injection
• API-based transaction flow for ease of use
• Text file-based configuration setting
• Supports Native integration with Verdi (HVP), Euclide IDE​

Debug and Analysis

• Verdi based protocol and performance analysis
• 1500+ Protocol checks with layer wise control
• Packet tracking at each layer along with coverage
• Debug ports and trace files (transaction, flit, control SKP​, message bus Interface and symbol logs)

Available on SoC Verification Kit (SVK) for interoperability and subsystem/SoC level verification using Synopsys IP 

Key Protocol Features

• Up to 128.0 GT/s data rate per lane with degraded modes and backward compatibility
• PAM4 signaling and Gray Coding
• Supports all encoding schemes & CRC
• Flit Mode and Non-Flit Mode​
• Equalization modes: No EQ, Bypass EQ, Full EQ & TS0 ordered set for 64GT/s and 128GT/s​
• Precoding support at 32GT/s, 64GT/s, and 128GT/s​
• Link Layer Initialization, Enumeration or bypass enumeration
• All Power Saving states
• SerDes PIPE, Original PIPE architecture, Low Pin Count and Legacy PIPE interfaces​
• DOE and IDE support​

Test Suite Features

• Test Groups based on the DUT Types: RC/EP/PHY/Retimer
• Seamless DUT integration with single, multi-link compile and topology file references.
• VIP & Verdi functional coverage framework for coverage driven verification of protocol features