The DesignWare® HPC Design Kit, part of Synopsys’ Foundation IP portfolio, is a suite of high-speed and high-density memories and logic libraries that allow SoC designers to optimize any processor cores for maximum speed, smallest area, lowest power, or an optimum balance of the three for their specific application. With optimized standard cells and SRAMs, the HPC Design Kit enables designers to optimize all of the processors on an SoC with a single package, reducing design costs and improving time-to-market. Optimized reference scripts and expert core implementation services are also available to help design teams achieve their processor and SoC design goals in the shortest possible time.
The latest HPC Design Kit allows SoC designers to optimize the DesignWare EV6x Embedded Vision Processor’s vector DSPs and convolutional neural network (CNN) engines. Depending on the requirements of the target application, designers using the HPC Design Kit for EV6x can optimize their implementation to achieve a 39% power reduction, a 10% reduction in area, or a 7% performance boost for their SoCs.
The HPC Design Kit is an add-on to the Duet Package of Embedded Memories and Logic Libraries.
HPC Design Kit Component Summary
DesignWare Embedded Memories and Logic Libraries are available for multiple foundries and process technologies, including GLOBALFOUNDRIES, SMIC, TSMC, and UMC.
DesignWare HPC Design Kit for TSMC 28HPM Datasheet
TSMC 16FF+ -Duet Embedded Memories and Logic Libraries Datasheet
TSMC 16FFC-Duet Embedded Memories and Logic Libraries Datasheet
TSMC 28HPC+ -Duet Embedded Memories and Logic Libraries Datasheet
TSMC 28HPC-Duet Embedded Memories and Logic Libraries Datasheet
Introducing the DesignWare HPC Design KitLearn how Synopsys' DesignWare HPC (High Performance Core) Design Kit, a single package containing high-speed and high-density memory instances and standard cell libraries, allow designers to optimize all their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power, or an optimum balance of the three. Hear about the latest results achieved through Synopsys' collaboration with Imagination on the Imagination PowerVR™ Series6 GPU core.
- One design kit for optimizing all processor cores on an SoC
- Includes ultra high-density memory compiler and more than 1000 new standard cells and memory instances
- Delivers up to 39% power reduction, a 10% reduction in area, or a 7% performance boost for SoCs using the DesignWare EV6x processor
- Delivers up to 10% performance improvement on CPU cores and up to 25% lower power with 10 percent area reduction on GPU cores such as the Imagination Technology PowerVR Series6 IP core
- Developed and validated with leading processor IP providers and customers
- Implement your optimized processor cores in as little as four to six weeks with Synopsys FastOpt services