Synopsys Die-to-Die IP Solutions

MCM Substrate or Silicon Interposer


Synopsys’ complete Die-to-Die IP solution includes 112G XSR and UCIe controllers and PHYs, with leading power, latency and die edge efficiency, for high-performance computing SoCs. The solution also includes HBI/AIB PHY. Synopsys UCIe IP, supporting standard and advanced packaging technologies, delivers up to 4Tbps bandwidth in a multi-module configuration. The UCIe controller enables an ultra-low latency link between two dies based on popular protocols and for compute-to-compute and compute-to-IO connectivity. Synopsys 112G XSR IP leverages high-speed SerDes technology up to 112G per lane for ultra and extra short reach links. The XSR controller includes a highly optimized FEC for a reliable, low latency link between two dies. Synopsys HBI/AIB PHY, supporting the AIB 2.0 standard, leverages wide-parallel bus technology and delivers 4Gbps per pin die-to-die connectivity with low latency.