DesignWare Die-to-Die IP Solutions

MCM Substrate or Silicon Interposer

Overview

Synopsys’ complete DesignWare® Die-to-Die IP solution includes controller, 112G USR/XSR and HBI PHYs with leading power, latency and die edge efficiency, for high-performance computing SoCs targeting hyperscale data center, AI, and networking applications. The configurable Die-to-Die controller includes an optional FEC and replay mechanism and seamlessly interoperates with the 112G USR/XSR PHY providing a low latency, reliable, NOC-to-NOC solution with support for full PAM-4 PHY bandwidth. The USR/XSR PHY IP leverages high-speed SerDes PHY technology up to 112G per lane for ultra and extra short reach links. The High-Bandwidth Interconnect (HBI) PHY IP, leveraging wide-parallel bus technology, delivers 4Gbps per pin die-to-die connectivity with low latency.