The DesignWare® Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance computing SoCs. The controller interoperates with the DesignWare 112G USR/XSR PHY to deliver a complete Die-to-Die solution for a seamless connection between the on-die interconnect fabrics in both dies via the standard AXI or CXS ports. The DesignWare Die-to-Die Controller uses a FLIT-based architecture to minimize latency. It implements an advanced error detection and correction mechanism including Cyclic Redundancy Check (CRC) and optional latency-optimized Forward Error Correction (FEC) to reduce Bit Error Rate (BER) to a very low level for PAM-4 or NRZ PHY signaling. The embedded retry protocol enables very low latency, error free links between two dies.
The DesignWare Die-to-Die Controller optimizes system performance by supporting two configurations for coherent and non-coherent data traffic between the SoC bus and each die. The latency-optimized configuration interfaces with the SoC fabric via a FLIT-based interface (Arm® CXS) and the generic configuration leverages the Arm 4 AXI interface. The DesignWare Die-to-Die Controller can be extended to support any aggregate bandwidth between the two dies using bifurcation into multiple parallel links.
Glossary page: What is a Die-to-Die Interface?
Blog: How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity
DesignWare Die-to-Die Controller IP
Downloads and Documentation
- Low Latency controller for die-to-die connectivity
- Supports PAM-4 and NRZ PHY signaling mode in all data rates
- Reduces BER with optional FEC configurations
- Supports optional Arm® AMBA® AXI™ and CXS interfaces
- Supports coherent CXL/CCIX and noncoherent data traffic over die-to-die links
- Enables complete NoC-to-NoC interface between two dies
|D2D Controller addon for D2D SR112G PHY with CXS interface||STARs