A die-to-die interface, just like any other chip-to-chip interface, creates a reliable data link between two dies.
The interface is logically divided into a physical layer, link layer, and transaction layer. It establishes and maintains the link during chip operation, while presenting to the application a standardized parallel interface that connects to the internal interconnect fabric.
Link reliability is guaranteed by the addition of error detection and correction mechanisms such as forward error correction (FEC) and/or cyclic redundancy code (CRC) and retry.
The physical layer architecture can be SerDes-based or parallel-based.
- A SerDes-based architecture includes parallel-to-serial (serial-to-parallel) data conversion, impedance matching circuitry, and clock data recovery or clock forwarding functionality. It can support NRZ signaling or PAM-4 signaling for higher bandwidth, up to 112 Gbps. The primary role of a SerDes architecture is to minimize the number of I/O interconnects in simple 2D-type packaging like organic substrates.
- A parallel based architecture includes many low-speed, simple transceivers in parallel, each made of a driver and a receiver with forwarding clock techniques to further simplify the architecture. It supports DDR-type signaling. The primary role of a parallel architecture is to minimize power in dense 2.5Dtype packaging, like silicon interposers.