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HAPS-200 6 FPGA is the industry mainstream prototyping platform succeeding the de-facto industry standard that HAPS-100 4 FPGA established in the prototyping community. It can be used both in desktop and rack setups and scales from subsystems to chiplets to entire SoCs. HAPS-200 12 FPGA targets large prototype complexities for multi-die and AI applications. It is optimized for highest capacity density using rack mounted setups. Teams can develop on HAPS-200 6 FPGA systems and seamlessly scale to the powerful HAPS-200 12 FPGA racks - unlocking larger, more complex prototypes that include more of the design’s core processing.
What's New
Introducing Software-Defined Hardware-Assisted Verification: A New Benchmark for AI-Era Chip Design
Introducing Software-Defined Hardware-Assisted Verification
Accelerating AI Hardware: NVIDIA’s Journey with Synopsys HAPS Prototyping Solutions
Skymizer Reduces Verification Cycles for AI Accelerator IP Development by 33% with Synopsys HAPS Prototyping
Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles
Hardware-Assisted Verification: Scaling for Modern Semiconductor Complexity
Configurability for all Emulation and Prototyping Use Cases
HAPS-200 is built on an EP-Ready Hardware Platform that allows to reconfiguration to support ZeBu-200 synchronous clocking with ZeBu Software. Read more in our blog.
HAPS is ideal for IP RTL regressions for single-clock IPs. It allows fast execution of hardware and software. It is suitable for CPUs, GPUs, NPUs, and AI-accelerators.
HAPS can help validate low-level software drivers before software/hardware validation. Several debug capabilities allow developers to monitor and debug the execution software during the SoC system bring-up.
HAPS prototyping systems are used when synthesizable RTL source code of the ASIC/system-on-chip design is available, allowing designers to develop software, verify SoC hardware, and enable system validation before the silicon is taped out.
HAPS prototyping systems are capable of at-speed interface prototyping, due to the asynchronous capabilities of the HAPS ProtoCompiler. HAV Interface Prototyping Kit offers at-speed prototyping of Synopsys IP, allowing customers to run interoperability testing as well as compliance and certification.
Features & Benefits
- Performance: Up to 2X vs HAPS-100 Higher performance TDM; Higher host interface bandwidth, higher debug bandwidth
- Ease of re-cabling / reduced barrier to re-cabling for performance optimization
- Capacity scaling from single FPGA to multi-rack setup
- Ease of HW cabling setup and in-field replaceability of connectors
- Better Debug capacity and bandwidth; 4x vs HAPS-100
- Faster compile time maintains turnaround time for larger design sizes
- Compatibility with HAPS ecosystem
- Enable mixed systems: HAPS-200 + HAPS-100
- Maintain HT3 connectors for compatibility with existing accessories
- Form factor: better fit in rack environments, vertical PCB placement, and connectors on the side to optimize space and connectivity within racks
- Configurable for emulation utilizing Synopsys ZeBu Software
What Our Customers Are Saying
"With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions. Synopsys HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are looking forward to scaling our HAPS-200 deployment to take full advantage for our software development teams.”
Narendra Konda
|Vice President, Hardware Engineering, NVIDIA
“... HW-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness. FPGA-based emulation and prototyping play a central role in that effort by accelerating system bring-up and enabling earlier software development... Through joint optimization of Synopsys ZeBu with the AMD Vivado software stack, and by leveraging AMD EPYC processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster.”
Salil Raje
|Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
“Synopsys is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems.”
Kevork Kechichian
|Executive Vice President, Solutions Engineering, Arm
“Verifying hardware for our highly anticipated rack-scale AMD Helios solution... demands scalable and versatile verification platforms. The Synopsys SW-defined, HAV capabilities with EP-Ready hardware are critical to how we perform CPU, GPU and AI subsystems verification as well as full-system validation...
Alex Starr
|Corporate Fellow, AMD
“SiFive has a very large and configurable portfolio of RISC-V CPU and AI core IP. We extensively test our IP using software workloads on HAPS, which means we can run trillions of cycles per day. As next generation CPUs and AI cores become larger and more complex, we need to efficiently map them onto larger and more powerful FPGAs. With its EP-Ready hardware HAPS-200 offers us an FPGA platform to do full system emulation for reference platforms that scale from small microcontrollers all the way to large scale data center designs.”
Albert Huntington
|Vice President, Platform Engineering, SiFive
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The EP-ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation."
Alex Starr
|Corporate Fellow, AMD
