Synopsys delivers unmatched value by combining leading Interface IP with modeling, verification, and validation solutions for Virtualizer™, VCS®, ZeBu®, and HAPS®. IP and verification managers accelerate development, achieve compliance, and future-proof solutions with proven technology and robust validation.
The figure below using PCIe 7.0 as the protocol example, shows 10 different technologies—including the actual IP—that are necessary for accelerated development and full SW/HW USB IP Prototyping Kit system validation for protocols.
Synopsys Speed Adaptor with System Validation Server
Synopsys IP Prototyping Kits on HAPS-200
Product teams use Synopsys Transaction-Level Models (TLMs) as building blocks for virtual prototypes, covering performance-optimized processor and peripheral models. The industry’s broadest set of TLM models support hardware-software co-design and architecture design.
Synopsys Verification IP (VIP) provides engineers with the latest protocols and interfaces for verifying IP and subsystem integration into SoCs or multi-die systems supporting VCS simulation and simulation acceleration with ZeBu. VIP supports Arm® AMBA®, CCIX, Ethernet, MIPI®, PCIe®, USB, DRAM, FLASH, automotive, display, storage, and other protocols. Synopsys Test Groups offer field-of-use tied test suites for compliance and accelerated testbench development. VIP services enhance productivity and reduce risk.
SoC Verification Kits (SVKs) are preconfigured setups tailored to support Synopsys IP validation in customer subsystem or SoC environment. They combine protocol verification solutions with IP in target configurations and a testbench for quick environment setup. SVKs are delivered as tailored services for specific use-cases.
Synopsys Transactors accelerate verification of systems and interfaces, supporting VCS and ZeBu environments. They enable faster regression execution and seamless transition from simulation to emulation. Transactors allow flexible emulation model deployment on-prem or in the ZeBu Cloud.
Enable real application traffic to drive the DUT and validate in the application context. Support protocol-specific traffic generation and integrate with tester solutions like Keysight, Anritsu, and others. Infrastructure includes QEMU Virtual Machines for use with adaptors and the DUT.
Synopsys offers ZeBu PHY Models for validating SW that drives Synopsys PHY IP, customized for specific applications. Digital PHY Models include programmable registers for SW teams. SystemVerilog Real Number PHY Models (RNM) represent analog output for pre-silicon firmware validation, reducing schedule and risk for multi-die solutions.
Speed adaptors enable pre-silicon integration of DUT in real environments, supporting protocol-accurate speed adaptation. Often used for AI accelerators and server interaction via PCIe. Synopsys System Validation Server is a plug-and-play solution for protocol accurate host server for running customer applications with the DUT.
Synopsys IP Prototyping Kits (IPKs) stem from compliance tests for Synopsys controller RTL and Synopsys PHY silicon boards and are available as add-ons to HAPS prototyping. Synopsys IP customers use IPKs with HAPS for compliance and certification with standards organizations. Legacy protocols are supported in HAPS by standard interface cards.
HAPS prototyping solution offers an integrated prototyping flow. HAPS-200 is the flagship product and targets the most complex designs with the highest performance requirements. HAPS is supported by an ecosystem of third-party vendors from the Synopsys HAPS Connect program that provides accessory card interfaces for HAPS.