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Introduction
PCI Express® (PCIe®) is the backbone of high-performance computing, AI acceleration, and data center connectivity. With the industry’s rapid adoption of PCIe 6 and the anticipation of PCIe 7, IP and verification managers at semiconductor and hyperscalar companies face unprecedented challenges. Delivering robust, compliant, and validated PCIe systems faster than ever is essential to stay competitive. Synopsys leads the charge with proven PCIe IP and advanced verification platforms for hardware and software —VirtualizerTM virtual prototyping, VCS® simulation, ZeBu® emulation and HAPS® prototyping— helping customers reduce risk, accelerate schedules, and ensure standards compliance.
PCIe: Which Lane Are You On?
PCIe stands as one of the most critical interface protocol standards in the electronics industry. Thousands of engineers contribute to its ongoing standardization, reflecting just how vital it is for modern compute systems. PCIe serves as the primary connection between CPUs and AI accelerators, making demands on its performance higher than ever.
When I recently spent a weekend in Houston, Texas, I was reminded of what lane confusion can look like. Are Houston’s flyovers perhaps a model of the next generation of PCIe standards because they allow for so much more bandwidth than traditional cloverleaf intersections?
Figure 1: Complex, multi-lane traffic scenario
Implementing PCIe is a complex process. The specification for PCIe 6 alone spans more than 2,000 pages, detailing intricate requirements for controllers, PHYs, and system integration. Given this complexity, most design teams choose to license IP from trusted providers like Synopsys, leveraging proven PCIe 6 controller and PHY IP to avoid the pitfalls of developing from scratch.
At first glance, using off-the-shelf IP might seem to eliminate most verification tasks, especially logic errors within the IP itself. While this is true, the real challenge lies in integrating the PCIe IP into multi-die systems, both from a software and from a hardware perspective. Here, software teams and hardware verification teams encounter significant system-level challenges, from protocol compliance to real-world interoperability.
Whether you will be stuck in a PCIe traffic lane or leave you competition behind depends on picking the right partner and verification strategies to arrive first.
Bringing PCIe into a system isn’t just about plugging in a block of IP; it’s about ensuring flawless operation in a highly demanding environment. Data rates and interoperability requirements are increasing, and every new generation of PCIe raises the bar for bandwidth, latency, and system complexity. Even minor integration mistakes can lead to major issues, including costly re-spins and delayed product launches.
Verification teams must not only achieve first-pass silicon success but also ensure strict compliance with the ever-evolving PCI-SIG® standards. Missing compliance can result in failed interoperability and lost market opportunities. The complexity of modern, multi-die systems means that robust validation is mandatory—not just for catching bugs, but for guaranteeing reliable, high-speed performance in production.
Interface IP Solution Score: 10 out of 10!
Design teams tackling complex protocols like PCIe rely on a multi-step validation flow with multiple interface protocol solutions that need to be compliant to the protocol standard to ensure success. In the image below you can count 10 different technologies you will need to successfully implement a PCIe interface in your system. They all need to congruent with the IP for the specific protocol:
Figure 2: Compliant Protocol Solutions derived from Industry leading IP
On The Road to Success
Development teams are using 4 main methods to successful hardware, software and system validation and as part of this the 9 interface protocol solutions are being leveraged.
Virtual Prototyping: Getting the SW developers working before there is RTL
Software developers face the same uphill challenge to update their drivers for a new protocol version and integrated them with the OS as the hardware engineers face to integrate the IP with the rest of the SoC. Traditionally they must wait until they have silicon with the actual interface IP, but over the last decade many companies have pushed their SW teams to start much earlier – shift left – with pre-silicon platforms. The earliest form and the fastest (SW guys love speed!) is a virtual prototype, a model of the final system that behaves like the final system enabling driver software to access registers. For the last 15 years Synopsys has developed virtual models of the Synopsys Interface IP, making the assembly of a Virtual Prototype a straightforward drag-and-drop exercise in the Virtualizer platform. 1,000s of SW engineers worldwide are using a Virtualizer Development Kits (VDKs) for their pre-silicon software development.
Simulation: Verification of the IP or the system?
After integrating PCIe IP —often into a network-on-chip (NoC) infrastructure— verification teams use Verification IP (VIP) and test suites to run initial validation. While simulation is foundational, it can be time-consuming, especially if IP and VIP come from different vendors. Contrary to the misconception that VIP coming from a different vendor (“second pair of eyes”) will ensure finding more bugs, the use of VIP is not meant to find bugs in the high-quality IP for which you pay your supplier, but funding bugs in the system integration. At Synopsys, IP and VIP and developed by different teams that are working hand-in-glove from the early days of each standard. This tight collaboration saves customers using both VIP and IP from Synopsys costly bring-up time and hence improves the quality of system-level validation in each verification schedule. Customers who want to save even more time and resources can also rely on Synopsys System Validation Kits (SVK) that deliver out of the box pre-integrated VIP-IP combinations along with a suite testing their specific IP configuration, which for a highly configurable protocol such as PCIe is a multi-month schedule benefit.
Emulation: Debug the design or the protocol solution?
Once functional correctness and protocol compliance are achieved in simulation; it’s time to bring up the interface with real software and run payloads. This step is best performed on high-performance emulation platforms like Synopsys ZeBu. Here, teams connect IP to their environment either virtually via transactors or physically using speed adapters. These virtual and physical protocol solutions must be compliant to the PCIe standard allowing for the IP to connect to an external test bench representing PCIe traffic. Components of the Synopsys PCIe IP are directly used to implement transactors and speed adaptors in a standard compliant way. This eliminates verification team risk of using a protocol solution that is not based on the industry leading PCIe IP. Teams don’t want to waste precious emulation time to find out that the protocol solution has a PCIe bug while their design was correct all along the way. It is also important that the emulation model of the PCIe subsystem enables complete software validation of drivers, hence often the PHY model must be added with exact register configuration matching the customer IP configuration.
Virtual system adaptors connect the design under test with an external software development environment running virtual machines. This allows for SW teams to develop drivers and perform guest OS integration prior to silicon.
Synopsys customers benefit from the internal alignment between the IP team and emulation that ensure that the transactors delivered for the customer projects match the specific IP configuration. Mismatches could take months to debug and are very painful when IP and emulation platform do not come from the same vendors. Once you must get the lawyers involved to sign NDAs, projects can slow down a lot!
Prototyping: Running much faster is not good enough
There are two schools of thoughts in the industry about why prototyping matters:
- Running faster than emulation (specifically if you have a slow emulator) is good enough.
- Prototyping benefit is connecting the protocol at speed to the external environment. Design teams taking on the risk of silicon respin and long silicon bring-up times, if they forgo the at-speed validation.
Why is this important? Imagine you are a product manager, and your design team tells you that they bought the IP from a reputable IP vendor and you are good to go to market. You will be in for a bad surprise!
You only know if you are compliant with the protocol standard and you can be certified if you test your entire system together with a production use environment. This step is crucial for avoiding costly silicon re-spins and confirming system-level interoperability before tape-out. Synopsys customers benefit from the HAPS performance as well as from IP Prototyping Kits that contain the Synopsys controller IP and the Synopsys PHY silicon, ready for use with HAPS.
PCIe 6 Gold System: Industry Reference for Schedule and Risk Reduction
The Synopsys PCIe 6 HAPS-based implementation is now recognized as the industry reference system - the PCIe Special Interest Group Gold System1. Any customer who wants the PCIe SIG standard certification stamp needs to connect their system to the PCIe 6 Gold System.
This endorsement means customers using Synopsys IP and verification solutions customers are best positioned to achieve schedule and risk reduction. Immediate access to proven reference designs, including Synopsys IP Prototyping Kits accelerates development and validation, streamlining compliance and interoperability testing.
Figure 3: Synopsys PCIe 6 Gold System built with HAPS-100 Prototyping
Mature, widely adopted solutions from Synopsys provide a trusted foundation for next-generation PCIe deployments. Validation uncertainty is minimized, enabling teams to innovate confidently.
Futureproofing for PCIe 7
PCIe 7.x brings new challenges, but Synopsys is engaged with many early adopters. Even though the standard is not finalized and test silicon just came out2, Synopsys offers flexible IP and scalable HAV platforms to help teams start validation early. Synopsys’ collaboration with PCI-SIG ensures solutions are always aligned with evolving standards.
Partnering with Synopsys for PCIe 7.x means access to first-to-market IP, industry reference systems, and ongoing technical support—so customers can future-proof their designs and maintain a competitive edge.
Value for the Market
Synopsys delivers unmatched value by combining leading Interface Protocol IP with Virtualizer, VCS, ZeBu and HAPS Interface Protocol Solutions for schedule and risk reduction. IP and verification managers can confidently accelerate development, achieve compliance, and future-proof their solutions. With Synopsys, customers benefit from proven technology, robust validation, and IP leadership.
Two examples illustrate this. Microsoft3 reported at Synopsys Virtual Prototyping Day 2025 how they accelerate Windows driver development using Virtualizer Virtual Platforms. Google4 presented at the 2025 Synopsys User Group Conference in India about the protocol validation journey from simulation all the way to silicon and achieved 95% test case coverage with a WiFi device operating in a PCIe backplane connected to ZeBu through a PCIe speed adaptor.
If you want your interface protocols to work in real life, Synopsys is your best bet.
References
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