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In the global race to design advanced AI chips, Europe may lag behind the U.S. and Asia, but two universities are making bold strides to help the region catch up.
Following several months of collaboration and development, ETH Zurich and Technical University of Munich (TUM) recently taped out 7 nm chips — a first for European academia.
Supported by a full suite of Synopsys products through the Synopsys Academic & Research Alliances (SARA) program, the milestones are standout examples of the importance of university-industry partnership and provide a blueprint for AI and chip innovation in Europe.
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Tiny chips, huge stakes
Europe stands at a critical juncture in the global semiconductor industry. While the worldwide market was projected to expand by 11.2% in 2025, the growth forecast for Europe was a modest 3.4% — highlighting both challenges and opportunities for the region.
Major investment programs from the European Commission and its member states are actively addressing the situation. The Chips Joint Undertaking, for example, is working to expand Europe’s high-performance computing (HPC) capacity, accelerate the uptake of AI across key sectors, and bolster technology autonomy — all of which can deliver significant economic and security benefits.
But much work lies ahead, and given the semiconductor industry’s shortage of skilled engineers, academic research, innovation, and the cultivation of homegrown talent are critical pieces of the puzzle.
“AI is now driving the evolution of computing chips and brings enormous opportunity, so there is growing desire and momentum — not only in education, but also in research and industry — to close the gap between Europe and other regions,” says Prof. Dr. Luca Benini, chair of digital circuits and systems at ETH Zurich. “That’s why we are pushing hard to educate larger cohorts of students and equip them with the skills needed for the future of semiconductor design.”
Prof. Dr. Luca Benini (center) and students at ETH Zurich
Collaborating to solve a billion little problems
Programs like SARA and EUROPRACTICE provide universities with critical access to state-of-the-art design tools, process technologies, and other resources that empower researchers and professors to not only deepen education, but also drive innovation.
The 7 nm AI chip developed at ETH Zurich is the latest breakthrough. Known as the Picobello Project, it integrates 144 RISC-V cores and more than 10 MB of on-chip memory, all running at 1 GHz.
“We wanted to showcase our ability to design and demonstrate a very efficient solution for acceleration of inference in advanced technology,” says Benini. “The goal is to manage use cases like agentic AI in the cloud and at the edge, where we need extreme energy efficiency in a low power envelope.”
While Picobello is a test chip and not a product, it is a major contribution to the EuroHPC Joint Undertaking and its EUPILOT development project, which is aiming to advance all-European HPC accelerator technology.
Designed at ETH Zurich using Synopsys Fusion Compiler and open source RISC-V cores with tensor coprocessors, Picobello was the work of 20 researchers, including two from TUM who worked on location in Switzerland.
“We needed every bit of help that they could give us,” says Frank Gurkaynak, director of the Microelectronics Design Center at ETH Zurich and leader of the Picobello Project. “When we design chips that have a billion transistors, there are a billion little problems that must be solved. These inherently complex projects require large teams that are able to work together.”
Picobello 7 nm AI chip layout
Building knowledge
TUM is trying to increase the number of researchers available. The university recently established the Munich Advanced Technology Center for High-Tech AI Chips (MACHT-AI), which will train engineering, computer PhD, and graduate students on leading-edge chip design.
For Prof. Dr. Hussam Amrouch, founding director of MACHT-AI and chair of AI processor design at TUM, the new education and research center fills an urgent need in Europe. Multiple new advanced semiconductor manufacturing facilities are under construction or planned, including a 16 nm and 12 nm FinFET fab in Dresden, Germany, expected to come online by the end of 2027.
“We don’t have the knowledge or enough designers to really feed the market,” says Amrouch. “This is a much bigger problem than one group can solve, and it is where collaborations across Europe and with industry leaders such as Synopsys become essential to accelerate the mission. We don’t have the luxury of time to spend another five or six years catching up.”
TUM Prof. Dr. Hussam Amrouch with a chip die
Shrinking timelines
In addition to partnering on Picobello, TUM developed its own 7 nm chip with Synopsys tools and support. The 2 mm2 semiconductor was designed in just four months as an ultra-low-power multi-core AI accelerator for edge applications. The team leveraged the full Synopsys flow and ASIP Designer to fully customize and implement the chip’s RISC-V cores.
“There were a lot of unknowns and a lot of learning, and Synopsys was always super supportive through training, online sessions, and answering questions,” says Amrouch. “The collaboration made something possible that would seem impossible, taking only four months to design a 7 nm chip for the first time.”
ETH Zurich and TUM received their 7 nm chips in early 2026.
Prof. Dr. Luca Benini (far right) and others at ETH Zurich unpacking the Picobello chip
Taking a big step up
As ETH Zurich’s Picobello and TUM’s 2 mm2 chips were being fabricated, the researchers embarked on the next phase of development: extending the designs with silicon-proven, standards-based IPs.
“One of the main limitations of this design, like many academic designs, is that it doesn’t have access to input/output with adequate bandwidth and performance,” says Benini. “Even if you design a fantastic accelerator, if you don’t have a proper memory interface, it remains an academic exercise.”
ETH Zurich is now working to integrate its design with state-of-the-art Synopsys Interface IP solutions to address this limitation.
“It’s a big step up in complexity,” acknowledges Benini, but one that is vital to achieving the long-term ambition of an end-to-end design framework that integrates physical IPs with open source logic.
The bold vision is shared by Amrouch at TUM.
“To send graduates to the outside world with extremely high-quality skills that are in such high demand, we must move beyond classical tape-out, start to integrate commercial IPs, and leverage the latest technologies and flows used throughout the industry,” he says. “That’s really where the complex knowledge is, but it’s literally impossible without industry collaboration and support from Synopsys.”
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