Industry First Verification IP for Arm AMBA AXI-L: Simplifying Complex Verification in Evolving AXI Specifications

The Arm® AMBA® AXI (Advanced eXtensible Interface) has long set the standard for high-performance, low-latency bus protocols in modern SoC designs. With the debut of the AXI-L specification—building on the robust AXI-K foundation—Arm continues to drive innovation, offering new features that meet the demands of next-generation devices. As SoC complexity grows and time-to-market pressures intensify, the need for agile and scalable verification solutions becomes paramount.  

This blog explores how Synopsys delivers the industry’s first Verification IP (VIP) for Arm AMBA AXI-L, empowering designers to validate cutting-edge features efficiently and with confidence. 

ARM has introduced the latest AXI-L specification  in Aug 2025. The AXI-L specification introduces several transformative features designed to boost performance, efficiency, and security in advanced SoCs:

• Credited Transport: An innovative alternative to the traditional VALID/READY handshake, enables higher operating frequencies, improved traffic isolation via optional resource planes, and provides lowpower features through finegrained clock gating. Control is simplified using implicit credit return instead of explicit READY signalling.

• ARM compression technology (ACT): A block-based compression mechanism integrated with AXI5 to reduce memory bandwidth and storage usage while keeping the compression logic separate from processing elements. ACT improves performance and efficiency by reducing memory traffic, centralizing compression logic and maintaining strict correctness via Non-modifiable AXI semantics.

• PAS Signalling: PAS (Physical Address Space) signalling acts as a cleaner and more extensible replacement for the legacy AxPROT and AxNSE signals in AXI. This update is essential to support RME (Realm Management Extension) and Granular Data Isolation (GDI). This simplifies security attribute handling and makes AXI scalable for future security domains.

• RME-Granular Data Isolation (GDI): An extension to Arm RME that introduces new protected address spaces and enforcement rules to enable strong, cachesafe, finegrained memory isolation in AXI5 systems. GDI allows isolating memory per data flow, improving confidentiality and robustness for non-secure protected (NSP) and system Agent (SA) address space.

• Untranslated transactions v4: Extends AXI untranslated transactions to support Granular Data Isolation (GDI) and PCIe XT mode, enabling precise control of virtual and physical addressing, PAS, and security context in secure systems.

• CMO to the Point of Physical Storage (PoPS): PoPS introduces a new cache maintenance model that improves reliability in longrunning systems by ensuring writes reach the furthest point in the memory system, guaranteeing data is physically stored and protected from persistent memory errors.

• Wrapping burst restrictions: Introduces a new restriction option that limits WRAP bursts to cachelinesized, modifiable transactions in AXI to simplify system design and avoid complications in protocol conversion, caching, and interconnect logic.

The introduction of new features in rapidly evolving AXI specifications increases the timely verification capabilities. Developers need to meticulously validate new features at faster pace maintaining highest quality standards. 

• Verifying Credited Transport Semantics: AXI-L’s new transport model requires meticulous validation of credit allocation and handling under diverse traffic conditions. Synopsys VIP offers automated test sequences and robust coverage metrics to address these challenges.

• Security Attribute Propagation: PAS and GDI introduce new security domains. The VIP ensures correct propagation, detection of illegal downgrades, and comprehensive coverage for address-space transitions. 

• Manage Complexity: With AXI-L’s expanding capabilities, maintaining protocol compliance across configurations is daunting. Synopsys VIP’s integrated protocol checking and flexible configuration options streamline compliance verification.

• Backward Compatibility: Supporting legacy AXI implementations while adopting AXI-L features is simplified through Synopsys VIP’s backward-compatible architecture. 

• Debuggability and Coverage Closure: Achieving full coverage and debugging protocol issues in large SoCs requires robust VIP integration and deep observability. Advanced debug features with native Synopsys Verdi® integration enable fast root-cause analysis and coverage closure.

Synopsys AXI VIP delivers comprehensive verification across all AXI specifications. With added support for AXI-L, it provides an end-to-end solution that simplifies complex design verification through: 

• Support for the latest AXI-L versions while maintaining backward compatibility. 

• Native System Verilog UVM architecture for seamless integration and faster testbench development.

• Advanced performance analysis and robust debug for functional correctness.  

• Built in sequences, functional coverage, and verification plans for faster bring up and complete verification closure.

• Extensive configurability and integrated protocol checking to keep pace with rapidly evolving standards. 

Synopsys AXIL, together with CHIH and system monitor solutions, enables efficient verification of complex interconnect designs. By collaborating closely with early customers and ecosystem partners, Synopsys continues to evolve the standard architecture, integrating the latest specification features to support nextgeneration designs. 

Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems.