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About Verdi
The Verdi® debug and verification management platform is an all-encompassing solution designed to streamline and enhance your design entry, debug and verification management. With its robust capabilities and connection into the most popular signal database (FSDB), Verdi empowers you to plan, execute and determine coverage of your simulation regressions. Furthermore, Verdi offers world-class debug capabilities to provide you insight into all design and verification flows. Verdi includes powerful AI technology to automate difficult and tedious debug steps and easily navigate diverse and complicated design environments.
Key Benefits
Features
Core Debug
The Verdi system incorporates all technology and capabilities to exceed expectations for debug. Includes a full-featured waveform viewer, powerful waveform comparison engine, source code browser, state machine diagram viewer, simulator-independent protocol analysis, low-power analysis, and assertion analysis.
Testbench Debug
Includes support for SystemVerilog testbench, portable stimulus, and libraries, Universal Verification Methodology (UVM), to specialized testbench views, built-in message logging and UVM transaction recording interactive simulation control, transaction-level debug views are based on enhanced FSDB.
AI-Based Advanced Debug
The Verdi system offers automatic signal tracing across many clock cycles, temporal flow views, regression debug automation, and intelligent reuse of simulated waveforms.
Power-Aware
Analysis incorporating power intent with the UPF standard, visualizing and tracing the source of power-related errors as well as visualization of the power intent itself.
Performance Analysis
Performs system-level protocol-oriented performance analysis and debug. Identifies system bottlenecks and ensures key performance metrics like latency/bandwidth are on target.
Analog Mixed Signal
Provides comprehensive views of the overall design, debug for co-simulation of analog, digital and mixed-signal subsystems within a unified debug environment. Simplifies the process of co-simulation setup.
HW/SW Sync Debug
The Verdi system optionally enables embedded software-driven SoC verification with a synchronized multi-window view of both hardware and software. Combines instruction -accurate embedded processor, RTL, C and assembly visibility.
Emulation and Prototyping
The Verdi system directly links to ZeBu emulation and HAPS prototyping solutions for high-capacity, high-performance debug. It also provides analysis of fault simulation results from VC Z01X fault simulator.
Integrated Design Environment
Verdi enables the Euclide-based integrated design environment that features on-the-fly incremental compilation, elaboration, pseudo-synthesis and rule checking, integrated into an editor and provides feedback in seconds.
Verification Management
Works in conjunction with the VC Execution Manager for planning, managing compilation, regression test execution, data collection, reporting and tracking of the design verification process. Automates coverage-driven verification flows, tracks and collects regression results data in a relational database, and supports annotation of coverage results in Verdi.
Resources
Powerful, Leading Technologies for High Productivity
The Verdi system is built on the proven technologies and enhanced with AI to enable you to meet your verification and tape-out schedules. Productivity is boosted by unified technology that checks design entry in real time, manages regressions, collects data from Synopsys and third-party verification solutions, analyzes that data with AI techniques, and extends analytics with an API.
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