Verdi

Complete Debug System

The Verdi automated debug system incorporates all of the technology and capabilities you would expect in a debug system. In addition, the Verdi system combines advanced debug features with support for a broad range of languages and methodologies.

Core Features

The Verdi system provides the following fundamental debug features:

• Full-featured waveform viewer enables you to display and analyze activity over time
• Powerful waveform comparison engine allows you to isolate differences between fast signal database (FSDB) files
• Source code browser enables you to easily traverse between source code and hierarchy
• Flexible schematics and block diagrams give you the ability to display logic and connectivity using familiar symbols
• Intuitive bubble diagrams help you to reveal the operation of finite state machines

Advanced Features

The Verdi system also includes the following advanced debug features: 

• Automatic tracing of signal activity enables quick trace activity across many clock cycles with powerful behavior analysis technology 
  
• Temporal flow views provide a combined display of time and structure to help you rapidly understand cause and-effect relationships 
  
• Transaction-based debug with flexible transaction and message support for debug and analyzing designs at higher levels of abstraction
  
• Assertion-based debug with built-in support for assertions facilitates quick traversal from assertion failure to related design activity

SystemVerilog Testbench debug with:

• Full source code support for SystemVerilog Testbench (SVTB) and libraries, including Universal Verification Methodology (UVM), to ensure reusability and interoperability of testbench code
  
• Specialized views that help you understand testbench code, including declaration-based hierarchy browsing and navigation, class inheritance and relationship comprehension, and tracing
  
• Built-in message logging and automated UVM transaction recording capabilities, coupled with advanced visualization techniques, give you a complete picture of testbench activity in the post-simulation verification environment
  
• Full-featured interactive simulation control allows you to step through complex testbench code for more detailed analysis
  
• UVM-aware debug views allow users to explore verification results from specific UVM aspects like resources, factory, phase and sequence
  
• Transaction-level debug views are based on extended FSDB and support new transaction and relation data recording