Verdi

The Verdi system incorporates all technology and capabilities to exceed expectations for debug. Includes a full-featured waveform viewer, powerful waveform comparison engine, source code browser, state machine diagram viewer, simulator-independent protocol analysis, low-power analysis, and assertion analysis.

Includes support for SystemVerilog testbench, portable stimulus, and libraries, Universal Verification Methodology (UVM), to specialized testbench views, built-in message logging and UVM transaction recording interactive simulation control, transaction-level debug views are based on enhanced FSDB.

The Verdi system offers automatic signal tracing across many clock cycles, temporal flow views, regression debug automation, and intelligent reuse of simulated waveforms.

Analysis incorporating power intent with the UPF standard, visualizing and tracing the source of power-related errors as well as visualization of the power intent itself.

Performs system-level protocol-oriented performance analysis and debug. Identifies system bottlenecks and ensures key performance metrics like latency/bandwidth are on target.

Provides comprehensive views of the overall design, debug for co-simulation of analog, digital and mixed-signal subsystems within a unified debug environment. Simplifies the process of co-simulation setup.

The Verdi system optionally enables embedded software-driven SoC verification with a synchronized multi-window view of both hardware and software. Combines instruction -accurate embedded processor, RTL, C and assembly visibility.

The Verdi system directly links to ZeBu emulation and HAPS prototyping solutions for high-capacity, high-performance debug. It also provides analysis of fault simulation results from VC Z01X fault simulator.

Verdi enables the Euclide-based integrated design environment that features on-the-fly incremental compilation, elaboration, pseudo-synthesis and rule checking, integrated into an editor and provides feedback in seconds.

Works in conjunction with the VC Execution Manager for planning, managing compilation, regression test execution, data collection, reporting and tracking of the design verification process. Automates coverage-driven verification flows, tracks and collects regression results data in a relational database, and supports annotation of coverage results in Verdi.