Industry’s First PCIe 8.0 Verification IP: Powering AI, HPC, Automotive, and LLM Storage Innovations

The explosion of AI workloads, the relentless growth of high-performance computing (HPC), and the transformation of automotive systems are converging to redefine what’s possible in data movement and processing. With cars now equipped with dozens of high-resolution cameras generating aggregate bandwidths that rival data centers, and large language models (LLMs) demanding ever-bigger context windows—often requiring local storage of massive datasets—the pressure on I/O bandwidth and latency is unprecedented. 

To meet these requirements, the industry is moving toward PCI Express® 8.0, which doubles the data rate to an unprecedented 256 GT/s. Early verification of this next-generation standard is essential to accelerate software bring-up, streamline subsystem and SoC integration, and enable shift-left post-silicon validation. 

Synopsys is leading the charge with a major milestone: its PCIe® Verification IP (VIP) now supports all features in PCIe 8.0 Draft 0.3 and has successfully achieved end-to-end link-up at 256 GT/s. This breakthrough empowers design teams to validate PCIe Gen8 functionality early in the development cycle, reducing risk and speeding time-to-market for AI, HPC, and automotive platforms.

Since its debut in 2003, PCIe has been the backbone of high-speed data connectivity, evolving to meet the ever-increasing demands of CPUs, GPUs, accelerators, storage devices and autonomous vehicles. Each new generation has delivered a significant leap forward, while PCI-SIG has consistently ensured backward compatibility and focused on power efficiency, data integrity, and scalability.

• PCIe 3.0: 8 GT/s - high-performance computing
• PCIe 4.0: 16 GT/s - doubled throughput, fueling data center growth
• PCIe 5.0: 32 GT/s - enabled high-speed cloud workloads and scalable architecture
• PCIe 6.0: 64 GT/s - introduced FLITs and PAM4 signaling for unprecedented efficiency
• PCIe 7.0: 128 GT/s - addressed the bandwidth needs of AI and CXL™ memory pooling
• PCIe 8.0: 256 GT/s - enable high-performance, low-latency data movement for AI, HPC, and automotive systems

Beyond raw speed, PCIe 8.0 is engineered to tackle emerging challenges in data-intensive domains:

• Local storage for LLMs: As organizations strive to increase context windows for generative AI, storing and accessing terabytes of data locally becomes essential. PCIe 8.0’s massive bandwidth ensures that LLMs can retrieve and process data with minimal latency, unlocking new levels of AI performance and contextual understanding.
• Aggregate bandwidth in modern vehicles: With the adoption of advanced driver-assistance systems (ADAS) and autonomous driving, cars can host 16 or more cameras, each streaming at 8K resolution. The combined bandwidth can exceed 100 Gbps, necessitating ultra-fast, low-latency interconnects to process, analyze, and store data in real time for safety and navigation.

PCIe 8.0 introduces several advancements to enable the next level of system performance and scalability:

• Maximum 256 GT/s per lane, enabling terabyte-per-second system links
• Enhanced latency targets with <10 ns link-related latency adder
• Bandwidth efficiency within 2% of Gen6/Gen7 FLIT operation
• Robust backward compatibility with earlier PCIe generations
• Reliability target of FIT << 1 across large lane-count systems
• Channel reach equivalent to 128 GT/s with support for up to four Retimers
• Enhanced low-power behavior and L1 entry/exit latency comparable to Gen7
• Support for optical-friendly and cable-friendly infrastructures
• Enhanced L0p functionality for asymmetric TX/RX link widths, optimizing power consumption
• Flexible link split (2x8 or 1x16) at 256 GT/s for 1x16 for bandwidth optimization

These features are essential for AI inference and training platforms, memory disaggregation, advanced automotive SoCs, and high-density accelerator fabrics.

Synopsys PCIe 8.0 Verification IP stands out as the industry's first to fully support PCIe 8.0 Draft 0.3, having achieved successful end-to-end link-up at the full 256 GT/s data rate. Key features include:

• Full support for the 256 GT/s data rate and new encoding schemes
• Industry-first achievement of Gen8 link-up, validated in real-world scenarios
• Seamless backward compatibility from Gen1 through Gen8, ensuring broad applicability
• Early bring-up capabilities for high-bandwidth SoC architectures
• Advanced modeling for new 256 GT/s encoding and protocol behaviors

These capabilities enable design teams to uncover architectural issues early, conduct comprehensive performance validation, and accelerate both pre-silicon and post-silicon development cycles. Notably, early adopters in AI and HPC have reported significant reductions in integration time and improved confidence in system-level validation, thanks to the advanced verification flows enabled by Synopsys PCIe 8.0 VIP.

Synopsys recently demonstrated 256 GT/s data transmission PHY IP using existing silicon in our labs, showcasing the feasibility of PCIe 8.0 data-rates. This milestone highlights our ability to deliver high-speed PAM4 electrical capabilities with exceptional eye quality, proving readiness for next-gen bandwidth demands. 

“Synopsys is committed to empowering AI, HPC, and data center innovators by ensuring timely delivery and superior quality of PCIe 8.0 products. Our pioneering end to end protocol solutions and unwavering dedication to customer 8.0 are the driving forces behind this achievement." said Levent Caglar, Executive Director of Product & Business Management, HAV Interface Solutions at Synopsys.

As the pace of innovation in AI, HPC, automotive, and cloud computing accelerates, the need for robust, future-ready verification solutions becomes paramount. Synopsys, through close collaboration with industry partners and PCI-SIG, is empowering the next generation of system designers with the industry’s first PCIe 8.0 Verification IP. By delivering validated 256 GT/s link-up and comprehensive feature support, Synopsys PCIe 8.0 VIP provides a critical foundation for early adoption, faster time-to-market, and enduring system reliability in a rapidly evolving technology landscape. 

Synopsys is partnering with early customers and collaborators to enhance the standard architecture for their next-generation designs, incorporating new features now available with the latest specifications.  

Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems.