EDA
System
IP
SolvNetPlus
Training & Education
Optimizing Synopsys HAV solutions to find critical bugs at pre-silicon
Synopsys Hardware-assisted Test Solutions are advanced stimulus generation and checking tools for the most difficult verification problems. Incorporating industry-leading Threadmill, STING, and Imperas technologies, HW-assisted Test Solutions target verification of complex, many-core designs based on leading edge CPU architectures.
Combining deep technical knowledge in stimulus generation with the power of ZeBu and HAPS systems, HW-assisted Test Solutions maximize the ability to find critical bugs before a design reaches silicon. Portability of stimulus to simulation and silicon platforms enhances the overall value of this solution. HW-assisted Test Solutions increase verification productivity and ensure optimal use of hardware assets to produce a high-quality design.
Key Benefits
Features
- An integrated HAV solution for test generation, checking, debug, and coverage
- A verification solution for leading-edge CPU architectures supporting many cores, I/O devices, peripherals, SoCs, and systems
- Architectural and microarchitectural bug detection using reference models and multi-pass consistency checking
- A library of test stimulus targeting verification challenges such as cache and memory coherency
- Productivity gains through optimized test execution on hardware, integrated debug and coverage insights
- A methodology for reproducing post-Si defects on emulation for easier debugging
What's New
Resources
Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles
Hardware-Assisted Verification: Scaling for Modern Semiconductor Complexity
