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Synopsys is unleashing a new wave of advanced chip designs with the availability of its Interface and Foundation IP portfolio on the TSMC N3E FinFET process. High-performance computing, mobile, and multi-die system creators can now use industry-leading silicon-proven IP to optimize power, performance, and area across their designs. TSMC's N3E process extends its 3nm family with enhanced power, performance and yield, meeting the demands of workload-intensive applications like high-performance computing, AI, and mobile.
TSMC's and Synopsys' long history of collaboration to advance semiconductor innovation addresses the increasingly complex challenges of emerging applications. First-pass silicon success of Synopsys Interface IP using Foundation IP on the TSMC N3E process technology enables designers to reduce their integration risk and meet their stringent power, performance and area targets.
Successful Synopsys IP test chip tape-out accelerates time-to-market of SoC designs
High-quality Interface IP enables low-risk integration of the most widely used protocols
Comprehensive Foundation IP meets stringent application requirements
The Synopsys Multi-Protocol 112G PHY IP on TSMC N3E is part of Synopsys’ high performance multi-rate transceiver portfolio for high-end networking and high-performance computing applications. The 1-112Gbps PHY IP supports multiple electrical standards, including PCI Express 6.0, 400G/800G Ethernet, CCIX, CXL2.0/3.0, JESD204, CPRI and more. The placement-aware 112G PHY IP integrates seamlessly with the Synopsys MAC and PCS, delivering a complete 200G/400G/800G Ethernet solution.
The Synopsys LPDDR5X/5/4X Controller on TSMC N3E is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. The Synopsys LPDDR5 Controller seamlessly integrates with the Synopsys Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory.
The Synopsys DDR5 PHY IP on TSMC N3E supports JEDEC standard DDR5 SDRAMs and memory modules operating up to 8400Mbps servicing server, enterprise, AI, and networking applications. Synopsys DDR5 IP is part of the complete Synopsys DDR interface solution that includes PHY IPs, controllers, IME security modules, IP subsystems, verification IP, and IP prototyping kits.
The Synopsys PCIe 5.0 PHY IP on TSMC N3E is part of the complete solution for PCI Express PCIe 5.0 consisting of silicon-proven digital controllers, PHY IPs, integrity and data encryption (IDE) security modules, and verification IP. Our PHY IP enables real-time data connectivity with low-latency and high-performance for cloud computing, storage, and AI SoCs.
The Synopsys USB-C 3.2/DisplayPort 1.4 PHY IP on TSMC N3E is targeted for integration into SoCs that support connections to high-definition (HD), 2K, 4K, and 8K Ultra High Definition (UHD) display from mobile devices, set-top boxes and other applications requiring fast data transfers and output of high-resolution content. Synopsys offers complete solutions for USB/DisplayPort IP implementations, including PHY IPs, controllers with HDCP 2.3 security modules, verification IP, and IP subsystems to accelerate design cycles.
The Synopsys MIPI C-PHY IP/D-PHY IP on TSMC N3E enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY IP operates at 6.5Gb/s per lane and 6.5Gs/s per trio respectively for a maximum speed of 44.5Gb/s, and supports C-PHY IP v2.0 and D-PHY IP 2.1.
Synopsys Foundation IP for TSMC N3E process, including embedded memories and logic libraries, enables designers to achieve optimal power, performance, and area for their SoCs. Synopsys Foundation IP on TSMC process technologies is extensively proven in silicon with billions of units shipping in volume production, reducing design risk and speeding time-to-market.
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