Synopsys UFS Host Controller IP

The Synopsys Universal Flash Storage (UFS) Host Controller IP is a standardbased serial interface engine for implementing the JEDEC UFS interface in compliance with the JEDEC UFS, UFS Host Controller Interface(UFSHCI) standards. The Synopsys UFS Host Controller IP is a high-performance, low-power interface that is primarily used in applications where data is stored on embedded non-volatile mass storage memory devices. The UFS Host Controller IP integrates the UFS host controller application layer with a pre-configured Synopsys MIPI® UniPro protocol stack that is optimized for UFS host applications.

Given the sensitive data stored on many mobile devices, smartphones in particular, robust security is an important consideration. Synopsys UFS Host Controller IP was designed with robust security features. To meet the demand for encryption of data stored on the smartphone’s local storage (contacts, e-mails, etc.), inline encryption (IE) has been added to the UFSHCI specification. Synopsys’ implementation of the AES-XTS encryption/decryption block, supporting 128- and 256-bit keys, is part of the data pipeline, ensuring transparency without any performance loss as it does not take any additional CPU cycles. In addition, Replay Protected Memory Block (RPMB) ensures that device memory regions can only be accessed by authenticated host applications. The Synopsys Host Controller supports the necessary commands and data structures.

A standard-based synchronous bus system, such as AXI, connects the IP to the rest of the system-on-chip (SoC). This bus is connected to the register interface and the Direct Memory Access (DMA) interface of the IP. The register and data structure implementation is based on the UFSHCI specification and is used by the UFS Host Controller’s DMA engine. Leveraging industry standards in the UFS Host Controller ensures compatibility and performance.