DesignWare IP for PCI Express (PCIe) 5.0


Synopsys’ DesignWare IP complete solution for PCI Express (PCIe) 5.0 operating at 32GT/s data rates enables real-time data connectivity with low-latency and high-performance for cloud computing, storage, and AI SoCs. The solution consists of silicon-proven digital controllers, PHYs, IDE Security Modules, and verification IP.

The low-power, compact IP has been used in dozens of PCIe 5.0 designs with successful tape outs and demonstrated proven interoperability with a range of products in the industry, making it the industry's lowest-risk solution supporting the key features of the PCIe 5.0 Revision 1.0 and PIPE 5.x specifications, including SerDes architecture and 64-bit PIPE. Synopsys, the industry’s leading IP provider for PCIe, is an active member of the PCI-SIG standards organization, actively contributing to the development and adoption of the PCIe specification. Overall, the DesignWare IP for PCI Express has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market.

The PCI Express 5.0 Superhighway Is Wide, Fast, and Ready for Your Designs

With the announcement of the PCIe 6.0 high-speed interface specification—64 GT/s—the design starts are imminent. But if you are looking for something that is deploying with great performance and bandwidth along with a nascent ecosystem that will support it, the PCIe 5.0 specification at 32 GT/s doesn’t disappoint.