DesignWare IP for PCI Express (PCIe) 5.0


Synopsys’ complete DesignWare IP solution for PCI Express (PCIe) 5.0 operating at 32GT/s data rates enables real-time data connectivity with low-latency and high-performance for cloud computing, storage, and AI SoCs.

The low-power, compact IP has been used in dozens of PCIe 5.0 designs with successful tape outs and demonstrated proven interoperability with a range of products in the industry, making it the industry's lowest-risk solution supporting the key features of the PCIe 5.0 Revision 1.0 and PIPE 5.x specifications, including SerDes architecture and 64-bit PIPE. Synopsys, the industry’s leading IP provider for PCIe, is an active member of the PCI-SIG standards organization, actively contributing to the development and adoption of the PCIe specification. overall, the DesignWare IP for PCI Express has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market.

Controller IP for PCI Express 5.0

The silicon-proven PCIe 5.0 controller IP offers flexible datapath support from 32-bit to 512-bit with lane widths ranging from x1 to x16, providing maximum throughput required for data intensive applications. Synopsys' PCIe 5.0 controller offers industry’s first production-proven 512-bit architecture, providing flexible options to optimize latency and timing closure for SoCs. For best latency performance, the Synopsys controller has demonstrated 1GHz timing closure in real customer applications. The controller IP can be user-configured to support Dual Mode, Endpoint, Root Port, and Switch applications in your choice of datapath widths, PIPE interface widths, and operating frequencies, helping to optimize for size, power, latency, and throughput, and include a rich feature set with extensive ECN support. Advanced RAS features including data protection, extensive debug capabilities, error injection and statistical monitoring helps designers successfully debug and resolve PCI Express linkup issues.

PHY IP for PCI Express 5.0

The PCIe 5.0 PHY IP with leading power, performance, and area is available in a range of advanced FinFET process nodes for a wide range of foundries. It is a multi-protocol PHY that supports a continuous data rate operation from 1.25Gb/s to 32Gb/s. Delivering exceptional signal integrity and jitter performance that exceeds the PCIe standards electrical specifications, the PHY meets the needs of high-speed chip-to-chip, board-to-board, and backplane interfaces. In addition, the DesignWare IP for PCIe 5.0 supports the new Compute Express LINK (CXL) and CCIX v1.1 specifications, allowing more than 36dB channel loss across PVT variations for long reach applications. 

Verification IP for PCI Express 5.0

Synopsys VC Verification IP (VIP) for the PCI Express provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of PCIe 5.0 designs. It accelerates testbench development, providing easy-to-use APIs for generating PCIe traffic.