The multi-channel Synopsys PHY IP for PCI Express® (PCIe®)5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

Synopsys IP PHY IP for PCI Express 5.0 and CXL

Highlights

Products

Downloads and Documentation

Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
Adaptive receiver equalizer with programmable settings
Supports lane margining at the receiver
Supports L1 substate power management
Power gating
Embedded bit error rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40°C to 125°C junction temperatures
Supports flip-chip packaging

10G PHY for Differential Buffer, TSMC N5, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, A00 SS5LPE x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF G2, x6, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, NCS,TSMC N5 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SF4X, x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS 4LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS5LPE x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPU x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPU x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N6 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G PHY for Differential Buffer, TSMC N5, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc5ff_ns
Version:	3.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer for TSMC 5FF (PHY Version:3.07a_d1) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 5FF (PHY Version: 3.07a) ( TXT )
Download:	dwc_diffbuf_tsmc5ff_ns
Product Code:	F690-0

Description:	10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc7ff_ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer Databook for TSMC 7FF (PHY Version: 2.09a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 7FF (PHY Version: 2.09a) ( TXT )
Download:	dwc_diffbuf_tsmc7ff_ns
Product Code:	C522-0

Description:	PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc7ff_x4ns
Version:	2.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databook DesignWare® Cores PCIe 5 PHY x4 for TSMC 7FF Databook (PHY Version: 2.01a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for TSMC 7FF Reference Manual (PHY Version: 2.01a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for TSMC 7FF Release Notes (PHY Version: 2.01a) ( TXT )
Download:	dwc_pcie5phy_ncs_tsmc7ff_x4ns
Product Code:	G230-0

Description:	PCIe 5.0 PHY, A00 SS5LPE x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_a00_ss5lpe_x2ns
Version:	1.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x2 for SS 5LPE Databook (PHY Version: 1.07a) ( PDF \| HTML ) PCIe 5.0 PCS for DesignWare® Cores PCIe 5.0 PHY x2 for SS 5LPE Databook (PCS Version: 1.52a) ( HTML ) PCIe 5.0 PCS for DesignWare® Cores PCIe 5.0 PHY x2 for SS 5LPE PHY/PCS Wrapper Databook (PCS Version: 1.52a) ( PDF ) Reference Manual DesignWare® Cores PCIe 5 PHY x2 for SS 5LPE Reference Manual (PHY Version: 1.07a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x2 for SS 5LPE Release Notes (PHY Version: 1.07a) ( TEXT )
Download:	dwc_pcie5phy_a00_ss5lpe_x2ns
Product Code:	H222-0

Description:	PCIe 5.0 PHY, NCS,TSMC N5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc5ff_x4ns
Version:	3.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 x4 PHY for TSMC 5FF Databook (PHY Version: 3.02a_d1) ( PDF \| HTML ) PCIe 5.0 PCS for DesignWare® Cores PCIe 5.0 PHY x4 for TSMC 5FF/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for TSMC 5FF Reference Manual (PHY Version: 3.02a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for TSMC 5FF Release Notes (PHY Version: 3.02a) ( TEXT )
Download:	dwc_pcie5phy_ncs_tsmc5ff_x4ns
Product Code:	F833-0

Description:	PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc6ff_x4ns
Version:	2.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x4 for TSMC 6FF Databook (PHY Version: 2.02a_d2) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for TSMC 6FF PHY/PCS Wrapper Databook (PCS Version: 1.48a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for TSMC 6FF Reference Manual (PHY Version: 2.02a_d1) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for TSMC 6FF Release Notes (PHY Version: 2.02a) ( TXT )
Download:	dwc_pcie5phy_ncs_tsmc6ff_x4ns
Product Code:	G102-0

Description:	PCIe 5.0 PHY, SF4X, x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_sf4x_x1ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	PCIe 5.0 PHY, SS 4LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss4lpp_x4ns
Version:	2.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.30a (Raw PCS >= 1.17)) ( PDF \| HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5.0 PHY x4 for SS 4LPP Databook (PHY Version: 2.01a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for SS 4LPP (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5.0 PHY x4 for SS 4LPP Reference Manual (PHY Version: 2.01a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5.0 PHY x4 for SS 4LPP Release Notes (PHY Version: 2.01a) ( TXT )
Download:	dwc_pcie5phy_ss4lpp_x4ns
Product Code:	F472-0

Description:	PCIe 5.0 PHY, SS5LPE x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss5lpe_x4ns
Version:	1.04b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.13)) ( PDF \| HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x4 for SS 5LPe Databook (PHY Version: 1.04b) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for SS5LPE PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for SS 5LPe Reference Manual (PHY Version: 1.04b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for SS 5LPe Release Notes (PHY Version: 1.04b) ( TEXT )
Download:	dwc_pcie5phy_ss5lpe_x4ns
Product Code:	F416-0

Description:	PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss7hpp_x4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY ATE Testbench (Doc Version: 1.0) ( PDF ) DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databook DesignWare® Cores PCIe 5 PHY for Samsung LN7HPP Databook (PHY Version: 1.03a) ( HTML \| PDF ) Release Notes DesignWare® Cores PCIe 5 PHY for Samsung LN7HPP Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	dwc_pcie5phy_ss7hpp_x4ns
Product Code:	E128-0

Description:	PCIe 5.0 PHY, SS8LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpp_x1ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x1 for SS 8LPP Databook (PHY Version: 1.02a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x1 for SS8LPP PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x1 for SS 8LPP Reference Manual (PHY Version: 1.02a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x1 for SS 8LPP Release Notes (PHY Version: 1.02a) ( TXT )
Download:	dwc_pcie5phy_ss8lpp_x1ns
Product Code:	F475-0

Description:	PCIe 5.0 PHY, SS8LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpp_x2ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x2 for SS 8LPP Databook (PHY Version: 1.02a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x2 for SS8LPP PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x2 for SS 8LPP Reference Manual (PHY Version: 1.02a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x2 for SS8LPP Release Notes (PHY Version: 1.02a) ( TXT )
Download:	dwc_pcie5phy_ss8lpp_x2ns
Product Code:	F476-0

Description:	PCIe 5.0 PHY, SS8LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpp_x4ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x4 for SS8LPP Databook (PHY Version: 1.02a_d2) ( PDF \| HTML ) DesignWare® Cores PCIe 5 PHY x4 for SS8LPP PHY/PCS Wrapper Databook (PCS Version: 1.52a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for SS 8LPP Reference Manual (PHY Version: 1.02a_d1) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for SS8LPP Release Notes (PHY Version: 1.02a_d1) ( TXT )
Download:	dwc_pcie5phy_ss8lpp_x4ns
Product Code:	F477-0

Description:	PCIe 5.0 PHY, SS8LPU x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpu_x2ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	PCIe 5.0 PHY, SS8LPU x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpu_x4ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc5ff_x4ns
Version:	2.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 x4 PHY for TSMC 5FF Databook (PHY Version: 2.05a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for TSMC 5FF PHY/PCS Wrapper Databook (PCS Version: 1.55a; PHY Version: 2.05a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for TSMC 5FF Reference Manual (PHY Version: 2.05a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 for TSMC 5FF Release Notes (PHY Version: 2.05a) ( TEXT )
Download:	dwc_pcie5phy_tsmc5ff_x4ns
Product Code:	E465-0

Description:	PCIe 5.0 PHY, TSMC N6 x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc6ff_x2ns
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc6ff_x4ns
Version:	2.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.13)) ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 x4 PHY for TSMC 6FF Databook (PHY Version: 2.02a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for TSMC 6FF PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 x4 PHY for TSMC 6FF Reference Manual (PHY Version: 2.02a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe5 PHY x4 for TSMC 6FF Release Notes (PHY Version: 2.02a) ( TXT )
Download:	dwc_pcie5phy_tsmc6ff_x4ns
Product Code:	E967-0

Description:	PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc6ff_x6ns
Version:	2.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x6 for TSMC 6FF Databook (PHY Version: 2.00a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x6 for TSMC 6FF PHY/PCS Wrapper Databook (PCS Version: 1.52a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x6 for TSMC 6FF Release Notes (PHY Version: 2.00a) ( TXT )
Download:	dwc_pcie5phy_tsmc6ff_x6ns
Product Code:	F981-0

Description:	PCIe 5.0 PHY, TSMC12FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc12ffc_x2ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x2 for TSMC 12FFC Databook (PHY Version: 3.01a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x2 for TSMC 12FFC PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x2 for TSMC 12FFC Reference Manual (PHY Version: 3.01a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x2 for TSMC 12FFC Release Notes (PHY Version: 3.01a) ( TXT )
Download:	dwc_pcie5phy_tsmc12ffc_x2ns
Product Code:	G545-0

Description:	PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc12ffc_x4ns
Version:	2.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.13)) ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY for TSMC 12FFC Databook (PHY Version: 2.05a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 Databook (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 for TSMC 12FFCReference Manual (PHY Version: 2.05a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe5 PHY for TSMC 12FFC Release Notes (PHY Version: 2.05a) ( TXT )
Download:	dwc_pcie5phy_tsmc12ffc_x4ns
Product Code:	E214-0

Description:	PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc16ffc_x4ns
Version:	2.01b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY for TSMC 16FFC Databook (PHY Version: 2.01b_d1) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY Databook (PCS Version: 1.48a) ( PDF \| HTML ) Datasheet Synopsys IP PHY IP for PCI Express 5.0 and CXL ( PDF ) Release Notes DesignWare® Cores PCIe5 PHY for TSMC 16FFC Release Notes (PHY Version: 2.01b) ( TXT )
Download:	dwc_pcie5phy_tsmc16ffc_x4ns
Product Code:	D347-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x4ns
Version:	3.00b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.13)) ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( HTML ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) DesignWare® Cores SerDes PHY Temperature Sensor Procedure (Doc Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 5 PHY x4 Gen2 for TSMC 7FF Databook (PHY Version: 3.00b) ( PDF \| HTML ) PCIe 5 PHY PCS for the DesignWare® Cores PCIe 5 PHY Gen2 x4 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.54a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare® Cores PCIe 5.0 PHY x4 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.53a) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x4 Gen2 for TSMC 7FF Reference Manual (PHY Version: 3.00b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x4 Gen2 for TSMC 7FF Release Notes (PHY Version: 3.00b) ( TXT )
Download:	dwc_pcie5phy_g2_tsmc7ff_x4ns
Product Code:	F457-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x6, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x6ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.40a) ( PDF \| HTML ) DesignWare® Cores High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.20a ( PDF \| HTML ) DesignWare® Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS >= 1.17)) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20a Raw PCS >= 1.14)) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databook DesignWare® Cores PCIe 5 PHY x6 for TSMC 7FF Databook (PHY Version: 3.00a_d1) ( PDF \| HTML ) Reference Manual DesignWare® Cores PCIe 5 PHY x6 for TSMC 7FF Reference Manual (PHY Version: 3.00a_d1) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 5 PHY x6 for TSMC 7FF Release Notes (PHY Version: 3.00a) ( TXT )
Download:	dwc_pcie5phy_g2_tsmc7ff_x6ns
Product Code:	H050-0