Synopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®)5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies. The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.
Synopsys IP PHY IP for PCI Express 5.0 and CXL
Highlights
Products
Downloads and Documentation
- Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
- Adaptive receiver equalizer with programmable settings
- Supports lane margining at the receiver
- Supports L1 substate power management
- Power gating
- Embedded bit error rate (BER) tester and internal eye monitor
- Built-in Self Test vectors, PRBS generation and checker
- IEEE 1149.6 AC JTAG Boundary Scan
- Supports -40°C to 125°C junction temperatures
- Supports flip-chip packaging
| 10G PHY for Differential Buffer, TSMC N5, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, SS 4LPP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, SS5LPE x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, SS8LPP x1, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, SS8LPP x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, SS8LPP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC12FFC x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation | STARs | Subscribe |
| Description: | 10G PHY for Differential Buffer, TSMC N5, North/South (vertical) poly orientation |
| Name: | dwc_diffbuf_tsmc5ff_ns |
| Version: | 3.07a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_diffbuf_tsmc5ff_ns |
| Product Code: | F690-0 |
| Description: | 10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation |
| Name: | dwc_diffbuf_tsmc7ff_ns |
| Version: | 2.09a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_diffbuf_tsmc7ff_ns |
| Product Code: | C522-0 |
| Description: | PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ncs_tsmc7ff_x4ns |
| Version: | 2.01a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ncs_tsmc7ff_x4ns |
| Product Code: | G230-0 |
| Description: | PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ncs_tsmc6ff_x4ns |
| Version: | 2.02a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ncs_tsmc6ff_x4ns |
| Product Code: | G102-0 |
| Description: | PCIe 5.0 PHY, SS 4LPP x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ss4lpp_x4ns |
| Version: | 1.03c |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ss4lpp_x4ns |
| Product Code: | F472-0 |
| Description: | PCIe 5.0 PHY, SS5LPE x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ss5lpe_x4ns |
| Version: | 1.02a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ss5lpe_x4ns |
| Product Code: | F416-0 |
| Description: | PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ss7hpp_x4ns |
| Version: | 1.03a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ss7hpp_x4ns |
| Product Code: | E128-0 |
| Description: | PCIe 5.0 PHY, SS8LPP x1, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ss8lpp_x1ns |
| Version: | 1.02a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ss8lpp_x1ns |
| Product Code: | F475-0 |
| Description: | PCIe 5.0 PHY, SS8LPP x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ss8lpp_x2ns |
| Version: | 1.02a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ss8lpp_x2ns |
| Product Code: | F476-0 |
| Description: | PCIe 5.0 PHY, SS8LPP x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_ss8lpp_x4ns |
| Version: | 1.02a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_ss8lpp_x4ns |
| Product Code: | F477-0 |
| Description: | PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_tsmc5ff_x4ns |
| Version: | 2.03b |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_tsmc5ff_x4ns |
| Product Code: | E465-0 |
| Description: | PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_tsmc6ff_x4ns |
| Version: | 2.02a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_tsmc6ff_x4ns |
| Product Code: | E967-0 |
| Description: | PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_tsmc6ff_x6ns |
| Version: | 2.00a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_tsmc6ff_x6ns |
| Product Code: | F981-0 |
| Description: | PCIe 5.0 PHY, TSMC12FFC x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_tsmc12ffc_x2ns |
| Version: | 3.00a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_tsmc12ffc_x2ns |
| Product Code: | G545-0 |
| Description: | PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_tsmc12ffc_x4ns |
| Version: | 2.05a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_tsmc12ffc_x4ns |
| Product Code: | E214-0 |
| Description: | PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_tsmc16ffc_x4ns |
| Version: | 2.01b |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_tsmc16ffc_x4ns |
| Product Code: | D347-0 |
| Description: | PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie5phy_g2_tsmc7ff_x4ns |
| Version: | 3.00a |
| ECCN: | 5E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie5phy_g2_tsmc7ff_x4ns |
| Product Code: | F457-0 |
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