DesignWare PHY IP for PCI Express 5.0 and CXL

The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®)5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

DesignWare IP PHY IP for PCI Express 5.0 and CXL

Highlights

Products

Downloads and Documentation

Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
Adaptive receiver equalizer with programmable settings
Supports lane margining at the receiver
Supports L1 substate power management
Power gating
Embedded bit error rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40°C to 125°C junction temperatures
Supports flip-chip packaging

PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss7hpp_x4ns
Version:	1.03a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY ATE Testbench (Doc Version: 1.0) ( PDF ) DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 1.9a) ( PDF ) Databook DesignWare Cores PCIe 5 PHY for Samsung LN7HPP Databook (PHY Version: 1.03a) ( HTML \| PDF ) Release Notes DesignWare Cores PCIe 5 PHY for Samsung LN7HPP Release Notes (PHY Version: … ( PDF )
Download:	dwc_pcie5phy_ss7hpp_x4ns
Product Code:	E128-0

Description:	PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc5ff_x4ns
Version:	2.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 1.9a) ( PDF ) Databook DesignWare Cores PCIe 5 x4 PHY for TSMC 5FF Databook (PHY Version: 2.00a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe5 PHY x4 for TSMC 5FF Release Notes (PHY Version: 2.00a) ( TXT )
Download:	dwc_pcie5phy_tsmc5ff_x4ns
Product Code:	E465-0

Description:	PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc12ffc_x4ns
Version:	2.02a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) DesignWare Cores Multi-Protocol PCIe5 PHY ATE Testbench Application Note (Doc … ( HTML \| PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 1.9a) ( PDF ) Databooks DesignWare Cores PCIe 5 PHY for TSMC 12FFC Databook (PHY Version: 2.02a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare Cores PCIe 5.0 PHY (PCS Version: 1.46_2) ( PDF ) Release Notes DesignWare Cores PCIe5 PHY for TSMC 12FFC Release Notes (PHY Version: 2.02a) ( TXT )
Download:	dwc_pcie5phy_tsmc12ffc_x4ns
Product Code:	E214-0

Description:	PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc16ffc_x4ns
Version:	2.00b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 1.9a) ( PDF ) Databooks DesignWare Cores PCIe 5 PHY for TSMC 16FFC Databook (PHY Version: 2.00b) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare Cores PCIe 5.0 PHY Databook (PCS Version: 1.47a) ( PDF ) Datasheet DesignWare IP PHY IP for PCI Express 5.0 and CXL ( PDF ) Release Notes DesignWare Cores PCIe5 PHY for TSMC 16FFC Release Notes (PHY Version: 2.00b) ( TXT )
Download:	dwc_pcie5phy_tsmc16ffc_x4ns
Product Code:	D347-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x4ns
Version:	2.00b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) DesignWare Cores Multi-Protocol PCIe5 PHY ATE Testbench Application Note (Doc … ( HTML \| PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) Databooks DesignWare Cores PCIe 5 PHYx4 Gen2 for TSMC 7FF Databook (PHY Version: 2.00b) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare Cores PCIe 5.0 PHY Databook (PCS Version: 1.47a) ( PDF ) Release Notes DesignWare Cores PCIe 5 PHY for TSMC 7FF Release Notes (PHY Version: 2.00b) ( TXT )
Download:	dwc_pcie5phy_g2_tsmc7ff_x4ns
Product Code:	F457-0

Description:	PCIe 5.0 PHY, TSMC7FF x16, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc7ff_x16ns
Version:	1.05a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF )
Download:	dwc_pcie5phy_tsmc7ff_x16ns

Description:	PCIe 5.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc7ff_x2ns
Version:	1.01a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 1.9a) ( PDF ) Databook DesignWare Cores PCIe 5 Two-Lane PHY for TSMC 7FF Databook (PHY Version: 1.01a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe 5 Two-Lane PHY for TSMC 7FF Release Notes (PHY … ( PDF )
Download:	PCIe-50-PHY_TSMC_N7_x2

Description:	PCIe 5.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc7ff_x4ns
Version:	2.00b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores 32G PHY IP Integration Review Checklist Application Notes (Doc … ( PDF \| HTML ) DesignWare Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( PDF ) DesignWare Cores Multi-Protocol PCIe5 PHY ATE Testbench Application Note (Doc … ( HTML \| PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 1.9a) ( PDF ) Databooks DesignWare Cores PCIe 5 PHY for TSMC 7FF Databook (PHY Version: 2.00b) ( PDF ) DesignWare Cores PCIe 5 PHY x4 for TSMC 7FF Databook (PHY Version: 2.00b) ( HTML ) PCIe 5.0 PCS for the DesignWare Cores PCIe 5.0 PHY Databook (PCS Version: 1.47a) ( PDF ) Release Notes DesignWare Cores PCIe 5 PHY x4 for TSMC 7FF Release Notes (PHY Version: 2.00b) ( TXT )
Download:	dwc_pcie5phy_tsmc7ff_x4ns