DesignWare PHY IP for PCI Express 5.0 and CXL

The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®)5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

DesignWare IP PHY IP for PCI Express 5.0 and CXL

Highlights

Products

Downloads and Documentation

Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.1 specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
Adaptive receiver equalizer with programmable settings
Supports lane margining at the receiver
Supports L1 substate power management
Power gating
Embedded bit error rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40°C to 125°C junction temperatures
Supports flip-chip packaging

PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss7hpp_x4ns
Version:	1.01a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	PCIe-50-PHY_SS_7HPP_x4
Product Code:	E128-0

Description:	PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc16ffc_x4ns
Version:	1.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) Multi-Protocol 32G PHY ATE Testbench ( PDF ) SERDES PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 5 PHY for TSMC 16FFC ( PDF ) PCIe 5.0 PCS for the DesignWare Cores PCIe 5.0 PHY ( PDF ) Register databook with change bars ( PDF ) Datasheet DesignWare IP PHY IP for PCI Express 5.0 and CXL ( PDF ) Release Notes DesignWare Cores PCIe5 PHY for TSMC 16FFC ( TXT )
Download:	PCIe-50-PHY_TSMC_16FFC_x4
Product Code:	D347-0

Description:	PCIe 5.0 PHY, TSMC7FF x16, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc7ff_x16ns
Version:	1.01a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	PCIe-50-PHY_TSMC_N7_x16
Product Code:	D754-0

Description:	PCIe 5.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc7ff_x2ns
Version:	1.01a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	PCIe-50-PHY_TSMC_N7_x2
Product Code:	D991-0

Description:	PCIe 5.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc7ff_x4ns
Version:	1.01a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) Multi-Protocol 32G PHY ATE Testbench ( PDF ) SERDES PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 5 PHY for TSMC 7FF ( PDF ) PCIe 5.0 PCS for the DesignWare Cores PCIe 5.0 PHY ( PDF ) Release Notes DesignWare Cores PCIe 5 PHY for TSMC 7FF ( TXT )
Download:	PCIe-50-PHY_TSMC_N7_x4
Product Code:	E003-0