The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®)5.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY meets the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.
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DesignWare IP PHY IP for PCI Express 5.0
Downloads and Documentation
- Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
- Adaptive receiver equalizer with programmable settings
- Supports lane margining at the receiver
- Supports L1 substate power management
- Power gating
- Embedded bit error rate (BER) tester and internal eye monitor
- Built-in Self Test vectors, PRBS generation and checker
- IEEE 1149.6 AC JTAG Boundary Scan
- Supports -40°C to 125°C junction temperatures
- Supports flip-chip packaging
|PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation||STARs