DesignWare Multi-Port Switch IP for PCI Express

The DesignWare® Multi-Port Switch IP for PCI Express implements the switch logic required to build a switch or bridge device leveraging the Synopsys DesignWare Switch Port IP and DesignWare Embedded Endpoint Controller IP for PCI Express. The configurable and scalable IP supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1, 1.1 and PHY Interface for PCI Express (PIPE) specifications. The high-quality, synthesizable IP is available in your choice of datapath widths, PIPE interface widths, operating frequencies, and many configuration parameters, all working together to enable designers to optimize their applications for size, power, latency and throughput. The DesignWare Multi-Port Switch IP for PCI Express is customized to integrate quickly and easily into system-on-chip (SoC) designs with conservative timing suitable for a wide range of ASICs. With the optional DesignWare Embedded Endpoint Controller IP, designers can simplify their designs and reduce latency and area by bringing applications inside their SoCs. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.

For more information and to get started on your next design project, contact the DesignWare IP team.

DesignWare IP for PCI Express Complete Solution Datasheet
DesignWare Multi-Port Switch IP for PCI Express

 

Highlights
  • Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE specifications
  • One upstream port and configurable multiple downstream ports
  • Ports configurable by
    • Lanes: x1 – x16
    • Max Speed: Gen1/Gen2/Gen3/Gen4/Gen5
    • Bus width: 32/64/128/256/512
  • Supports DesignWare Embedded Endpoint Controller IP
  • Cut-thru buffer mode with small latency in fabric
  • Configurable number of virtual channels
  • Support of peer-to-peer traffic with non-blocking architecture
  • Support for Weighted Round Robin arbitration
  • Support of PCIe ordering model
  • Support for ECNs, like L1SS, LTR, Atomics
  • Made from Silicon-proven IP