How PCI Express Gives AI Accelerators a Super-Fast Jolt of Throughput

AI Is Everywhere—and So Is PCIe!

AI is fast becoming pervasive in chipsets, with more than 40% of chipsets projected to include AI hardware by 2030, according to GlobalData. The complexity of AI and machine learning (ML) workloads continues to grow. In fact, AI and ML training models double in size roughly every few months. To be effective, AI systems must be able to move large datasets through the AI development pipelines without sacrificing performance or latency. Consider these examples of bandwidth-intensive workloads:

• High-definition 4K and 8K video that requires more compute and memory
• High resolution and high dynamic range, which enable machine vision and real-time perception
• Multiple camera arrays and 4D sensing, which enable depth and motion inference

All of these trends point to the criticality of AI accelerators to deliver the parallel computation prowess needed for near-instantaneous responses by applications such as voice activation and highly automated vehicles. These high-performance machines can either take the form of a very large chip, such as Cerebras’ Wafer-Scale Engine (WSE) for deep-learning systems. Or, they can be GPUs, massively multi-core scalar processors, or spatial accelerators. The latter are individual chips that can be combined by the tens to hundreds, creating larger systems capable of processing large neural networks that often require hundreds of petaFLOPS of processing power. 

Synopsys, whose PCIe experts are also key contributors to the PCI-SIG consortium that writes the specifications for the PCIe buses, is an industry leader in PCIe IP and PCIe protocol verification aolutions (including Verification IPs). Our PCIe portfolio, with components featuring backwards compatibility, includes:

• Synopsys PHY IP, which optimizes digital equalization through adaptive digital signal processing (DSP) algorithms for efficient power across backplanes, network interface cards (NICs), and chip-to-chip channels
• Synopsys Controller IP with an architecture that’s tightly integrated with the Synopsys IDE Security IP Module, which includes multiple interfaces for the lowest latency and maximum throughput
• Synopsys Verification IP, which accelerates testbench development and has a built-in verification plan, sequences, and functional coverage
• Synopsys Protocol Interface Cards, In-Circuit, and Virtual Solutions for Synopsys ZeBu® emulation system and Synopsys HAPS® prototyping system, which enable software-driven system verification, performance analysis, certification, and compliance at pre-silicon

Beyond our end-to-end PCIe IP solution, our IP portfolio also includes memory, processor, and other interface IP that are beneficial for AI accelerators. Synopsys.ai™, our full-stack, AI-driven electronic design automation (EDA) suite, includes functions that can dramatically speed the design of specialized AI accelerators. On the verification side, AI SoCs requires faster hardware-assisted verification solutions at pre-silicon. Synopsys ZeBu Server 5 and HAPS® systems provide the industry’s fastest and highest capacity hardware-assisted verification (HAV) systems facilitating all system-level validation use cases for complex SoC designs.