EDA
System
IP
SolvNetPlus
Training & Education
Speed Software Development, Hardware Verification, and System Validation
Synopsys software-defined HAPS® prototyping systems accelerate software development, hardware verification, and system validation for everything from IP blocks to complete SoCs. Trusted across the electronic supply chain by IP, semiconductor, and system companies, HAPS combines proven hardware platforms, interface solutions, and optimized software. It delivers top performance and reliability with over 20 years of FPGA synthesis expertise from the Synopsys Synplify® product line.
What's New
Introducing Software-Defined Hardware-Assisted Verification
Introducing Software-Defined Hardware-Assisted Verification: A New Benchmark for AI-Era Chip Design
Accelerating AI Hardware: NVIDIA’s Journey with Synopsys HAPS Prototyping Solutions
Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles
Hardware-Assisted Verification: Scaling for Modern Semiconductor Complexity
Explore the Industry Leading Product Family
HAPS prototyping solution offers an integrated prototyping flow. HAPS-200 is the flagship product and targets the most complex designs with the highest performance requirements. HAPS is supported by an ecosystem of third-party vendors from the Synopsys HAPS Connect program that provides accessory card interfaces for HAPS.
Configurability for all Emulation and Prototyping Use Cases
ZeBu-200 is built on the Synopsys EP-Ready Hardware Platform that allows for software-defined upgrade to support HAPS-200 asynchronous clocking and HAPS ProtoCompiler, as well as the compliance and certification use case. Read more in our blog.
Users tend to do a lot of targeted functional verification as the RTL starts to come together. They need a platform that makes it easy and quick to port over their simulation environments and provide enough acceleration to cover the scenarios that are not ideal for simulation and formal environments. ZeBu’s simulation acceleration capabilities are utilized by industry’s major GPU, CPU, NPU, TPU providers along with other IP vendors in the networking, automotive sectors.
As RTL matures, users desire a platform that can provide orders of magnitude faster performance to cover long running suites. These regression suites serve the dual purpose of proving functional correctness, as well as getting closer to targets for coverage metrics. ZeBu’s transaction-based high-performance platform combines with its strong suite of industry’s latest Protocol Solutions (Transactor and Speed Adapters) to address these needs at some of the largest chip companies.
Starting from a reasonable level of RTL maturity, users start bringing up their software environments. There is a mix of bare-metal, low-level drivers and firmware, operating systems like Linux-Windows-Android, benchmark software application, general-purpose user applications that need to be brought up and proven functional. As the user persona evolves from being hardware-centric to a mix of hardware and software, ZeBu brings capabilities like Virtual Host Solutions to make the software developer feel at home. Combined with its superior performance, users can get very close to silicon like behavior.
As the designs near tape-out schedules, validation engineers get into a mode of mimicking their post-silicon lab environments. Their primary requirement is to enable hardware and software developers with a platform that could be used to serve as the highest-performance option in pre-silicon testing using real-world interfaces. They also want to build this platform as an option to reproduce and debug issues that they would encounter in the lab. Visibility into the design and being able to deterministically repeat those scenarios is key. ZeBu comes with a suite of strong debug technologies as well as a wide suite of speed adapters that have proven a capable partner for users to identify bugs and resolve them timely to not impact the customer’s time-to-market.
Users turn their attention to key design attributes of power and performance. They have long-running workloads that heavily exercise the DUT. By design, ZeBu can accurately model large number of clock domains prevalent in the modern SoC environments and yet provide the performance to execute these workloads.
HAPS prototyping systems are capable of at-speed interface prototyping, due to the asynchronous capabilities of the HAPS ProtoCompiler. HAV Interface Prototyping Kit offers at-speed prototyping of Synopsys IP, allowing customers to run interoperability testing as well as compliance and certification.
Synopsys Hardware-assisted Test Solutions are advanced stimulus generation and checking tools for the most difficult verification problems. HW-assisted Test Solutions maximize the ability to find critical bugs before a design reaches silicon, achieving compliance with the intended architecture.
What Our Customers Are Saying
"With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions. Synopsys HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are looking forward to scaling our HAPS-200 deployment to take full advantage for our software development teams.”
Narendra Konda
|Vice President, Hardware Engineering, NVIDIA
“... HW-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness. FPGA-based emulation and prototyping play a central role in that effort by accelerating system bring-up and enabling earlier software development... Through joint optimization of Synopsys ZeBu with the AMD Vivado software stack, and by leveraging AMD EPYC processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster.”
Salil Raje
|Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
“Synopsys is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems.”
Kevork Kechichian
|Executive Vice President, Solutions Engineering, Arm
“Verifying hardware for our highly anticipated rack-scale AMD Helios solution... demands scalable and versatile verification platforms. The Synopsys SW-defined, HAV capabilities with EP-Ready hardware are critical to how we perform CPU, GPU and AI subsystems verification as well as full-system validation...
Alex Starr
|Corporate Fellow, AMD
“SiFive has a very large and configurable portfolio of RISC-V CPU and AI core IP. We extensively test our IP using software workloads on HAPS, which means we can run trillions of cycles per day. As next generation CPUs and AI cores become larger and more complex, we need to efficiently map them onto larger and more powerful FPGAs. With its EP-Ready hardware HAPS-200 offers us an FPGA platform to do full system emulation for reference platforms that scale from small microcontrollers all the way to large scale data center designs.”
Albert Huntington
|Vice President, Platform Engineering, SiFive
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The EP-ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation."
Alex Starr
|Corporate Fellow, AMD
"Validating our multi-die design against real-world interfaces and scenarios with the high-performance HAPS prototyping platform enables us to optimize our design early on, with faster build times and more predictable results. Having a common hardware platform for different prototype models means we can shift the hardware to use on large or small models in real time, with reduced compute and storage resources and the ability to easily and quickly scale as our needs require."
Lam Ngo
|Principal Engineer, Microsoft
Resources
Skymizer Reduces Verification Cycles for AI Accelerator IP Development by 33% with Synopsys HAPS Prototyping
SiFive Discusses RISC-V SW Validation and Prototyping
Tools and Ecosystem
HAPS ProtoCompiler SW
HAPS ProtoCompiler software helps the prototyping team create the fastest performing implementation of their design on the HAPS prototyping hardware. It enables the prototype to find both the optimum partitioning between the FPGAs and the best connectivity using the HapsTrak3 cable. ProtoCompiler uses its proven timing-driven synthesis engine to create a performance optimized prototype. ProtoCompiler is used for runtime and debug, and feeds into the Synopsys Verdi® debug environment. Key features include:
| Performance Optimization | Constraint-driven partitioning and high-speed time-domain multiplexing maximize system clock performance |
| Optimized Partitioning | Optimizes partitioning between FPGAs and connectivity using HapsTrak3 cables |
| Timing-Driven Synthesis | Employs a proven timing-driven synthesis engine to handle complex clocking structures |
| High Capacity | Supports billion ASIC gate capacity for scalable SoC/ASIC projects |
| Flexible Debug Options | High-capacity storage options for single or multi-FPGA debug enhance observability and sample rates |
| Unified Debug Approach | Integrates with the industry-standard Verdi debug solution for efficient error analysis |
| Joint Debugging | Enables joint debugging by RTL verification engineers and prototypers, saving valuable project time |
| Hybrid Prototypes | Arm AMBA compatible transactor level interfaces facilitate hybrid prototype implementation |
HAPS Accessories
HAPS users benefit from a variety of add-on cards and accessories from Synopsys and HAPS Connect partners, including:
| MGB Board | Interfaces standard MGB cards with the HapsTrak connector. |
| GPIO+ Board | Facilitates debugging and basic interactivity through buttons and LEDs. |
| QSFP+ Board | Supports protocols like QSFP+, 40G Ethernet, and SAS. |
| HAPS Logic Analyzer Interface Board | Enables signal probing with standard logic analyzers. |
| LPDDR4 Memory Board | Aids in prototyping designs with LPDDR4 memories. |
| HapsTrak3 (HT3) Interconnect Board | Facilitates point-to-point connections between FPGAs. |
| External Clock Distribution Board | Synchronizes clocks across up to six HAPS systems. |
HAPS Ecosystem
The HAPS Connect program provides a wide range of third-party accessory boards and services that enhance the functionality of HAPS systems. If you're interested in becoming a HAPS Connect member to supply accessory cards to thousands of HAPS users, please contact us at [email protected].
e-Elements
- SOC_IO_HT3: This daughter board includes two micro-USB connectors, 20-pin Arm debug interface, 38-pin MICT, and 28-pin PMOD.
- SOC_SDNF_HT3: Features Micron NAND Flash and SDIO for access to general-purpose nonvolatile devices.
- SOC_NORF_HT3: Contains a TSOP56 NOR Flash device socket.
- FIREFLY_MGB: Supports up to 8 high-speed serial links over 2 FireFly cables.
- FMC_FIREFLY_HT3: Includes an FMC connector to interface with 3 FireFly connectors, supporting up to 10 high-speed links.
- USB3_HT3: Based on a TI TUSB1310 device with ULPI for USB 2.0 and a PIPE interface for USB 3.0 support.
Fidus
- Mantyss 32G: Contains the Xilinx Zynq UltraScale+ ZU19EG, supporting a quad-core Arm processor and up to 32Gbps links.
Gigafirm
- Giga Ninja: FPGA module board with an Intel MAX10 FPGA. I/O pins on a 2.54mm pitch header for various embedded applications.
- HTC-CCB: Used to cross-convert signals from the HT3 connector or cable.
- MGB-Firefly Module: A 12-lane MPO connector for short-reach applications up to 100m on OM3 multiple fiber cables.