Yes. The changes introduced with PCIe 6.0 affect all layers, creating increased verification complexity.
At the physical layer, 64GT/s speed support is achieved using PAM4 encoding. PCIe 6.0 introduces 256B FLIT, which demands certain packing rules for protocol packets into FLITs, increasing design complexity. It also brings in FEC complexity along with the existing CRC mechanism.
For backward compatibility reasons, 256B FLITs are supported at 2.5/5/8/16/32 GT/s speeds. This demands verification of FLIT mode at all supported speeds.
At the data link layer, addition of new DLLP types–namely optimized updatefc and link management, for exchanging link information, and change in sequence number/replay rules–demands in-depth verification of sequence numbering, FLIT replay command handshakes, and selective/full replay mechanisms to provide guaranteed FLIT transfer across to the link partners.
Along with the introduction of FLIT, new TLP framing rules are also defined, which requires extensive verification.
PCIe 6.0 also introduces a new power state L0p, which enables power reduction without impacting the traffic flow. Link management DLLPs are used to establish L0p handshake between link partners. This adds to the design complexity necessitating in-depth verification.
The disruptive nature of PCIe Gen6 specification will create new verification challenges not only for backward compatibility, bandwidth, and performance of the interface but also for dependent NVMe, SSD, and other PCIe-based storage technologies. Synopsys Verification IP (VIP) and test suite are designed to handle this verification complexity. Synopsys VIP is used to verify silicon-proven Synopsys IP.
In addition, running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors based on Synopsys IP enable fast verification hardware solutions including Synopsys ZeBu® emulation systems and Synopsys HAPS® prototyping systems for validation use cases.