PCI-SIG Developers Conference 2025

June 11-12, 2025

Santa Clara Convention Center
Santa Clara, CA
Event for PCI-SIG member companies

Why Attend?

Connect with developers and decision-makers focused on PCI Express technology. Join Synopsys at the event to explore how Synopsys’ Complete IP Solution for PCI Express can accelerate your time-to-market. With over two decades of experience spanning seven generations of PCI Express, Synopsys IP offers a high-quality, low-risk solution for your next design. 

Synopsys Booth

End-to-End PCIe 6.x Interoperability with Switch Provider

  • Successful PCIe 6.x interoperability with a leading switch provider, demonstrating root complex and endpoint 64GT/s link-up

Synopsys PCIe 7.0 IP extended Reach 40+db with ACC

  • Showcasing excellent 128 GT/s electrical performance in more than 40dB of cabling system with Semtech's OSFP and DAC assembly

 

Partner Booths

Anritsu's Booth
  • Featuring Synopsys PCIe 6.x IP solution successful interoperability with Anritsu’s Signal Quality Analyzer-R MP1900A RX LEQ using optical components
GRL's Booth
  • Demonstrating Synopsys PCIe 6.0 IP solution electrical performance with Anritsu’s Signal Quality Analyzer-R MP1900A and Keysight's real-time scope powered by GRL’s Shared Capacity Interoperability Software (GRL-SCIS)
Tektronix's Booth
  • Demonstrating Synopsys PCIe 7.0 PHY IP electrical transmitter performance using Tektronix's DPO70000SX real-time scope to measure our solution's key metrics such as SNDR/Jitter/TX EQ
Teledyne LeCroy's Booth
  • Featuring Synopsys PCIe 7.0 IP PHY IP with Teledyne LeCroy's tools showcasing transmitter equalization, eye diagram generation and measurement of SNDR, jitter, TxFFE and other critical characterization tasks  

  • Demonstrating PCIe 6.x interoperability testing with Teledyne LeCroy's Protocol Exerciser Summit M616 for PCI Express 6.x and Synopsys PCIe 6.x PHY and Controller IP

Viavi's Booth
  • Featuring Synopsys PCIe 6.x IP Solution successful link-up demonstrating 64GT/s with excellent performance

 

Presentations

PCI-SIG Architecture Overview

Richard Solomon, Principal Technical Product Manager, Synopsys | Wednesday, June 11 | 9:30 AM – 10:30 AM PT

L0p: Link Width Changes and Verification Challenges

Will Felten, R&D Architect, Synopsys | Wednesday, June 11 | 10:30 AM – 11:30 AM PT

Marketing Workgroup Panel: PCIe Technology Features Enabling Applications

Scott Knowlton, Sr. Director of Product Marketing, Synopsys | Wednesday, June 11 | 2:00 PM – 3:00 PM PT

FLIT Mode and Retry Verification: Pitfalls, Best Practices, and Solutions

Gaurav Manocha, Sr Staff Engineer for PCIe/CXL Transactor Development, Synopsys | Thursday, June 12 | 11:30 AM – 12:30 PM PT