EDA
System
IP
SolvNetPlus
Training & Education
Why Attend?
As the industry looks ahead to PCI Express 8.0, PCIâSIG DevCon 2026 is where architects and system designers come together to shape the future of highâperformance I/Oâfrom AI accelerators and scaleâup fabrics to disaggregated, dataâintensive systems. Synopsys brings decades of PCIe leadership across architecture, compliance, and interoperability, along with a complete PCIe IP solution including trusted, proven PHY and controller, IDE security, verification IP, interface validation and compliance solutions with Hardware-assisted Verification platforms.
Hear directly from Synopsys experts helping drive the PCIe ecosystem and learn how our endâtoâend solutions reduce risk, accelerate timeâtoâmarket, and help futureâproof designs as the industry prepares for PCIe 8.0.
Synopsys Booth
PCIe 8.0 Controller Simulation with Link Training
Featuring a PCIe 8.0 controller simulation with full link training and linkâup signaling, supporting preâsilicon architectural and protocol validation.
PCIe 8.0 TX Electrical Validation at 256 GT/s for NextâGeneration Systems
Featuring Synopsys PCIe PHY IP showcasing PCIe 8.0 TX electrical validation using Keysightâs N1010100A to demonstrate signal generation and measurement aligned with emerging PCIe 8.0 electrical requirements at 256 GT/s.âŻ
Partner Booths
Anritsu Booth
- Featuring Synopsys PCIe 7.0 PHY IP with Anritsu and Tektronixâs instrumentation, showcasing PCIe 7.0 electrical testing to support highâspeed signal characterization and validation at emerging PCIe 7.0 data rates.
GRL Booth
Featuring Synopsys PCIe 7.0 PHY IP with GRL PSâ testing software platform, showcasing PCIe 7.0 electrical validation to support signal integrity analysis and TX/RX electrical compliance testing.
Keysight Booth
Featuring Synopsys PCIe 7.0 IP, showcasing PCIe 7.0 TX eye measurements (EH, EW, SNDR, RLM) and RX BER testing on a PCIe 7.0 evaluation board to support early signal integrity characterization at 128âŻGT/s.
Featuring Synopsys PCIe 6.0 IP, showcasing end-to-end hardware linkup and performance from root complex to endpoint using Keysight equipment.
Samtec Booth
Featuring Synopsys PCIe 7.0 PHY IP, showcasing loopback performance using Samtecâs NovaRay I/O and 2âŻm cable system for AI/ML and dataâcenter applications.
Teledyne LeCroy Booth
- Featuring Synopsys PCIe 7.0 PHY IP with Teledyne LeCroy tools, showcasing transmitter equalization, eye diagram generation, and measurement of SNDR, jitter, and receiver performance.
Viavi Booth
- Featuring Synopsys PCIe 6.0 IP, Viavi Xgig, MACOM PCIe optical connectivity, and the Broadcom Atlas 3 switch, in an interoperability demonstration validating PCIe protocol compliance across electricalâtoâoptical implementations and illustrating the extensibility of the PCIe specification for future optical interconnect applications.
Presentations
Day 1 â Wednesday, May 6, 2026
Track 2: PCIâSIG Architecture
| Time | Session | Synopsys Speaker |
| 9:30 â 10:30 AM | PCIâSIG Architecture Overview | Richard Solomon, Technical Marketing Manager, Synopsys |
| 10:30 â 11:30 AM | PCI Express Basics | Richard Solomon, Technical Marketing Manager, Synopsys |
Track 3: Members ImplementationÂ
| Time | Session | Synopsys Speaker |
| 1:00 â 2:00 PM | System Level Correlation for PCIe 7 Over Optics | Monica Olvera, Product Manager, SerDes PHY IP, Synopsys |
| 2:00 â 3:00 PM | Enabling Scalable AI Infrastructure with PCIe Technology (MWG Panel) | Scott Knowlton, Sr. Director, Product Marketing, Synopsys (Moderator) |
Day 2 â Thursday, May 7, 2026
Track 2: PCIâSIG ArchitectureÂ
| Time | Session | Synopsys Speaker |
| 11:30 AM â 12:30 PM | PCIe Compliance: Protocol Deep Dive | Richard Solomon, Technical Marketing Manager, Synopsys |