PCI-SIG Developers Conference 2026

As the industry looks ahead to PCI Express 8.0, PCI‑SIG DevCon 2026 is where architects and system designers come together to shape the future of high‑performance I/O—from AI accelerators and scale‑up fabrics to disaggregated, data‑intensive systems. Synopsys brings decades of PCIe leadership across architecture, compliance, and interoperability, along with a complete PCIe IP solution including trusted, proven PHY and controller, IDE security, verification IP, interface validation and compliance solutions with Hardware-assisted Verification platforms

Hear directly from Synopsys experts helping drive the PCIe ecosystem and learn how our end‑to‑end solutions reduce risk, accelerate time‑to‑market, and help future‑proof designs as the industry prepares for PCIe 8.0.

Anritsu Booth

• Featuring Synopsys PCIe 7.0 PHY IP with Anritsu and Tektronix’s instrumentation, showcasing PCIe 7.0 electrical testing to support high‑speed signal characterization and validation at emerging PCIe 7.0 data rates.

GRL Booth

• Featuring Synopsys PCIe 7.0 PHY IP with GRL PS’ testing software platform, showcasing PCIe 7.0 electrical validation to support signal integrity analysis and TX/RX electrical compliance testing.

Keysight Booth

• Featuring Synopsys PCIe 7.0 IP, showcasing PCIe 7.0 TX eye measurements (EH, EW, SNDR, RLM) and RX BER testing on a PCIe 7.0 evaluation board to support early signal integrity characterization at 128 GT/s.

• Featuring Synopsys PCIe 6.0 IP, showcasing end-to-end hardware linkup and performance from root complex to endpoint using Keysight equipment.

Samtec Booth

• Featuring Synopsys PCIe 7.0 PHY IP, showcasing loopback performance using Samtec’s NovaRay I/O and 2 m cable system for AI/ML and data‑center applications.

Teledyne LeCroy Booth

• Featuring Synopsys PCIe 7.0 PHY IP with Teledyne LeCroy tools, showcasing transmitter equalization, eye diagram generation, and measurement of SNDR, jitter, and receiver performance.