PCI-SIG Developers Conference

PCI-SIG Developers Conferences 2022

Worldwide Locations

Asia
September 21, 2022 -- The Westin Tokyo
September 26, 2022 -- Grand Hyatt Seoul

Israel
October 24-25, 2022 -- Hilton Tel Aviv

Europe
October 27-28, 2022 -- The Westin Grand Munich

North America
June 21-22, 2022 -- Santa Clara Convention Center

Event for PCI-SIG member companies

Why Attend?

Connect with developers and decision makers focused on the PCI Express technology. Join Synopsys at the event to learn how to minimize your integration risk and confidently migrate to PCIe 6.0 with Synopsys IP. We have been and continue to be by your side, cultivating success with essential IP across six generations of PCI Express technology. See a variety of PCIe 5.0 and 6.0 product demos in our booth and our partners’ booths. We also invite you to network with our experts and attend our technical presentations.

Synopsys Demos

  • PCIe 6.0 Performance Across Lossy & Reflective Channels*: Silicon-proven Synopsys PHY IP for PCIe 6.0 on N5 process, showing excellent bit error rate over a PCIe 6.0 high-loss ISI channel in loopback mode
  • PCIe 6.0 End-to-End Hardware Linkup and Performance*: Synopsys controller and PHY IP for PCIe 6.0 in an end-to-end host to device system, showing successful link up performance metrics
  • Verification Closure with PCIe 6.0 VIP and Test Suites*: Synopsys Verification IP for PCIe 6.0 advanced protocol debugging capabilities

 

*All locations

Partner Demos

Anritsu*

  • Synopsys PHY IP for PCIe 6.0 pre-FEC and post-FEC loopback performance with Anritsu PAM-4 BERT and transmitter performance with Tektronix real time oscilloscope
  • Synopsys PCIe Controller and PHY IP for PCIe 5.0 transmitter link equalization test with Anritsu SI-BERT and Tektronix real time oscilloscope


Keysight**

  • Synopsys PHY IP for PCIe 6.0 showing transmitter eye linearity and receiver eye with PCIe 5.0 compliance channel and Jitter tolerance test


Samtec**

  • Synopsys PHY IP for PCIe 6.0 loopback performance over high-performance computing channels

 

*US, Tokyo and Munich locations

**US location only

Synopsys Presentations

Designing for Effective Use of PCIe 6.0 Bandwidth*

This presentation will discuss design choices and practices needed to make full use of that bandwidth across a variety of design points from x1 to x16 for both Endpoint and Root Port designs. Various potential pitfalls and performance scenarios will be covered and data presented from actual early implementations. 

Richard Solomon, Sr.Staff, Technical Marketing Manager

 

Protecting Data over PCIe in Cloud Computing*

This presentation discusses how security IP solutions integrated with the PCIe interface controllers make it faster and easier for designers to protect the SoCs against data tampering and physical attacks on every link while complying with the latest standards requirements.

Dana Neustadter, Sr. Marketing Manager, Synopsys Security IP

 

*US, Israel and Munich locations