TSMC OIP Forum North America

In-Person Presentations: 

• Design Technology Co-Optimization (DTCO) for Area Entitlement on TSMC N2/N2P using Synopsys Fusion Complier
• Efficient Timing Signoff for 2.5D and 3D Designs: Addressing Inter-Die Complexity at Scale
• Enhancing Analog Circuit Design: A Tutorial on AI-Driven, Layout-Aware Optimization Solutions
• Meeting SRAM and Foundation IP Requirements for Next-Generation Automotive SoCs on 5nm and 3nm FinFET Nodes
• Accelerating SoIC-X 3D-Stacked Advanced Package Design: From Architecture Planning and Optimization to Tapeout
• From Complexity to Clarity: Transforming advanced silicon design through Agentic AI

Virtual Presentations:

• Improve Performance, OCV Robustness, and Ease of Use with Flat-First H-Treee Insertion Flow for HPC Hierarchical Designs
• Silicon Results: TSMC CoWoS Interposer design with Synopsys SLM IP for Multi-Die Monitor, Test, and Repair
• Unlocking additional PPA gains on TSMC N2P Processes through AI-driven Metal Scheme Exploration
• AI-Driven Multi-Parameters Multi-Objectives Automatic Optimization For Transmission Line In High-Speed SerDes IP
• Optimal 3DIC Multiphysics Signoff with Timing, Power, and Thermal Convergence
• TSMC COUPE photonic integrated circuit co-design with custom verilog-A and PDK TMI models

Posters:

• Hierarchical EM-IR Signoff Methodology for large SoCs integrated in 2.5DIC Structures
• Power-Aware DFT - Taming IR-Drop for Robust Automotive SoC EMIR Sign-off
• Thermal aware design optimizations and signoff using RHSC electrothermal across process nodes/design