Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Evaluation →
Join Synopsys at the TSMC OIP Forum 2023 in multiple locations around the globe. Synopsys and TSMC have been collaborating to ensure customer success. We will have 16 in-person and online presentations. Register today!
Synopsys In-Person Presentations | North America
In-Person Presentations:
- Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
- A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs - Alchip and Synopsys
- Optimizing Compute Density for SiFive RISC-V processors in TSMC advanced nodes with Synopsys Fusion QuickStart Kits - SiFive and Synopsys
- Leveraging UCIe for High-Speed Stack Testing of Multi-Die Systems through Monitoring, Test & Repair (MTR) and HSAT IPs - Synopsys and TSMC
- Cisco Characterization using PrimeLib on Cloud for TSMC Advanced Node Libraries - Cisco and Synopsys
- Maximize Designer Productivity with AI-Driven EDA Vertical Stack
- Demonstrating Technology PPA Entitlement with TSMC’s N2 Technology on HPC Design Using Synopsys Fusion Compiler
- Synopsys AI-based Analog Design Migration Flow for TSMC Advanced Technologies
- Real Examples of 3D Heterogeneous Integration Using the TSMC 3Dblox Standard
- Achieving Ultra Low Power Designs on TSMC Advanced Nodes using Synopsys Foundation IP
- Virtual cross-die Coupling Capacitance Extraction Using Synopsys StarRC
On-Line Presentations:
- Enabling SoC level Full Path Current Density checks for ESD compliance
- Full Path Die-to-die ESD Interconnect Compliance Check in IC Validator PERC
- Synopsys SLM PVT Monitor IP readiness on TSMC N3E/N3P/N3AE
- Ensuring Reliability and Interoperability Using UCIe IP and CoWoS Technology
- Enabling the transition to terabit-scale Ethernet connectivity with Silicon-Proven 224G SerDes IP on TSMC’s 3nm Process
Why Attend?
Learn from OIP partners how to leverage their technology for your design challenges:
- Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22
- Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications
- Comprehensive design solutions for specialty technologies enabling ultra-low power, ultra-low voltage, analog migration, RF, mmWave, and automotive designs targeting 5G, automotive, and IoT designs
- Ecosystem specific TSMC reference flow implementations, P&R optimization, machine learn-ing to improve design quality and productivity, and cloud-based design solutions
- Successful , real-life applications of design technologies and IP solutions from TSMC's Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market
TSMC OIP Worldwide Events
Synopsys In-Person & Virtual Booth
Synopsys Booth #408
TSMC attendees are invited to visit the Synopsys booth to view the latest innovative technologies and chat with Synopsys experts live!
Booth topics include:
- Synopsys IP
- Fusion Design Family
- Design Signoff
- Unlock the Transformative Power of Artificial Intelligence
- Analog Design Tools
- Accelerate Physical Verification Closure
- Silicon Lifecycle Management
- Automotive Solutions - Design the future of automotive with Synopsys
