EDA
System
IP
SolvNetPlus
Training & Education
Why Attend?
Synopsys is pleased to join 2026 TSMC OIP as a Platinum Sponsor.
As a long‑standing TSMC ecosystem partner, we will be showcasing our latest design‑enablement technologies and silicon‑proven IP optimized for TSMC’s A16, A14, and N2P nodes and advanced packaging technologies.
We invite all attendees to visit Synopsys booth #508 to explore our demos and network with our experts.
In-Person & Virtual Presentations & Posters | North America
In-Person Presentations:
- Multiphysics-Aware Timing Signoff for AI and HPC Designs
Synopsys / Nvidia | 1:30pm-1:50pm - Methodology for Fmax-per-Watt Scaling in CPU-Centric Designs Using Advanced EDA and DTCO Techniques
Advanced Log Track / Synopsys | 2:50pm-3:10pm - Addressing Inter-Die STA Complexity for 3D Multi-Die Designs
Synopsys / Arm | 12:00pm-12:30pm - Automated Architecture-Phase PDN Prototyping Workflow to Advance Multi-Die Design
Synopsys / MediaTek | 3:50pm-4:10pm - Scaling AI Data Center Infrastructure Through Protocol-Agnostic Physical Design for Scale-Up Using 224G SerDes
AIchip Technologies | 1:50pm-2:10pm
Virtual Presentations:
- Improve Performance, OCV Robustness, and Ease of Use with Flat-First H-Treee Insertion Flow for HPC Hierarchical Designs, Keysight
- Silicon Results: TSMC CoWoS Interposer design with Synopsys SLM IP for Multi-Die Monitor, Test, and Repair, Nvidia
- Unlocking additional PPA gains on TSMC N2P Processes through AI-driven Metal Scheme Exploration, Nvidia
- AI-Driven Multi-Parameters Multi-Objectives Automatic Optimization For Transmission Line In High-Speed SerDes IP, Synopsys
- Optimal 3DIC Multiphysics Signoff with Timing, Power, and Thermal Convergence, TSMC
- TSMC COUPE photonic integrated circuit co-design with custom verilog-A and PDK TMI models
Synopsys In-Person Booth
View the latest innovative technologies and chat with Synopsys experts live!
EDA Flows Ready for Angstrom‑Scale Node:
Discover Synopsys’ AI-powered digital, analog and verification flows with multiphysics analysis, including production‑ready flows for TSMC A14, and certified flows for TSMC A16 and N2P designed for superior PPA and predictable closure.
Live demonstrations:
Stop by Booth #508 for hands‑on demonstrations showcasing Synopsys’ leading solutions spanning agentic AI for verification, analog and implementation, Multiphysics Fusion for analog, digital, photonics and multi-die, and silicon-proven IP.
Additional demonstrations will showcase Synopsys IP implemented on TSMC advanced process technologies, highlighting interoperability, signal integrity, power efficiency, and performance across next-generation AI workloads.
40GT/s UCIe Connectivity for Advanced Multi-Die Systems
See Synopsys' 40G UCIe IP operating in silicon on TSMC N3P technology. See measured receiver eye performance at 40GT/s, with the ability to operate at additional data rates, and learn how key signal integrity metrics are verified to assess transmitter performance and receiver margin in advanced multi-die designs.
224G Connectivity for Scale-Up and Scale-Out AI Infrastructure
See Synopsys 224G IP enabling the foundation for next-generation AI infrastructure, supporting emerging scale-up and scale-out architectures, including UALink, ESUN, Ultra Ethernet, and 1.6T networking, showcasing robust performance over extra long-reach connectivity.
Connect With Us:
Whether you are focused on high‑performance compute, AI acceleration, hyperscale infrastructure, mobile, or automotive silicon, Synopsys experts will be available to discuss design strategies and solutions that help you accelerate development on TSMC’s most advanced technologies.
We look forward to connecting with you at the Synopsys booth #508
TSMC OIP Worldwide Events
