ISSCC 2026

Visit our demos at the Synopsys Booth to see our latest innovations in action:

• AI-driven Analog Design Migration: Advanced FinFET and GAA technologies demand a meticulous approach to high-performance analog circuit design. Process technology complexity is advancing rapidly, presenting significant challenges in achieving design convergence in performance, area, and design for manufacturing. The Synopsys ASO.ai platform provides a comprehensive solution to all these challenges. The layout-aware, AI-Driven Design Optimization Solution drastically reduces the number of design iterations, thereby reducing the overall development cost, while simultaneously enhancing the quality of the output. The constraint-driven design migration efficiently helps migrate designs from one technology to another that save weeks of manual and iterative effort.

• Multiphysics Analysis for Analog & Mixed-Signal Design: The impacts of multiphysics interactions on analog and mixed-signal (AMS) circuits increase exponentially at higher frequencies, greater integration density, and advanced process nodes. Interactions between parasitic effects like thermal, electromagnetics, substrate noise, voltage drop, and more now often dominate the design time and design cost for advanced AMS circuits. Synopsys will be showing an incredibly broad portfolio of proven multiphysics simulation engines integrated with chip design tools to speed AMS design closure. This powerful multiphysics analysis platform accurately predicts circuit effects and quickly identifies the root cause of analog design issues.

• Accelerating Next‑Gen SoCs with High‑Performance, Silicon‑Proven IP: Showcasing Synopsys comprehensive, silicon‑proven IP portfolio engineered for advanced process technologies—from mature nodes down to cutting‑edge FinFET and GAA nanometer processes—and built to support the next generation of high‑performance standards including PCIe, CXL, DDR/LPDDR, Ethernet, USB, and MIPI. Optimized for key verticals such as AI, automotive, hyperscale data center, and consumer. Synopsys IP enables faster SoC integration, lower design risk, and industry‑leading PPA through pre‑validated subsystems, robust security features, and production‑proven delivery across thousands of designs.

You’ll also have the opportunity to connect with the Synopsys Academic & Research Alliances (SARA) team!

SARA partners with universities around the world to advance workforce development through cutting‑edge semiconductor and chip design education, empowering students and researchers with the skills needed to innovate across the entire chip design lifecycle. From digital design, analog/mixed‑signal, verification, and physical implementation to system‑level methodologies, SARA enables access to industry‑leading Synopsys tools and curricula that prepare talent for real‑world design challenges.

Whether you’re interested in how Synopsys collaborates with universities in your region, exploring new ways to strengthen chip design education and research, or looking to bring Synopsys EDA technology directly into your classroom or lab, visit the SARA team at the booth to discover how we can work together to cultivate the next generation of semiconductor and chip design innovators.