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Embedded World 2026

Stand 4-208

From Silicon to Systems: Re-engineering Engineering for Silicon Design and Software-Defined Systems

 

Join us at Embedded World 2026 to explore how Synopsys is empowering engineers to overcome the complexity of modern embedded systems. Synopsys solutions address the engineering challenges of software-defined systems development, accelerate time to market, reduce development costs, and mitigate safety, cybersecurity, IP protection and other risks associated with complex hardware and software systems through advanced analysis and virtualization.

 

Date/Time:
March 10-12, 2026

Location:
Nürnberg, Germany

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Synopsys Booth Expo | Hall 4-208

Synopsys solutions for Silicon Development, MBSE for Automotive and Aerospace & Defense, Cybersecurity, and Electronics Digital Twins for automotive software testing and automated system testing

RISV-V International Pavilion | Hall 5-119

Synopsys solutions to enable fast SoC development

Speakers & Highlights

Session: 3.7 Safety & Security - Reliable Architectures
Wed. March 11, 2026
10:30 - 11:00 AM PDT
Most Automotive MPU Strategies Have Hidden Safety Flaws, Is Yours One of Them?
  • Kevin Brand
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Hear from Kevin to explore current MPU validation challenges and testing processes on hardware but more importantly shows through case study, that virtual prototypes can give a significant boost in testing efficiency and test coverage.

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Session: 5.9 Software & Systems Engineering - Formal Verification
Wed. March 11, 2026
03:30 - 04:00 PM PDT
Usage of Formal Methods in Embedded Software Development to Automate Test Case Generation Based on Model Coverage Gaps.
  • Vincent Rossignol
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This presentation introduces a Model Coverage Assistant (MCA), which improves software verification efficiency by automating coverage analysis tasks at model level. MCA applies formal methods to identify untestable points or generate test cases, reducing manual effort and saving up to 70% in V&V time.

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Session: 8.4 Use Cases for Embedded - Development Processes
Thu. March 12, 2026
09:30 - 10:00 AM PDT
Informed Systems Engineering Decision-making Through SysML v2 Modelling with Architecture Simulation.
  • Dr. Bernhard Kaiser
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This session presents a methodology that integrates system architecture modelling with architecture-level simulation to close this gap. The workflow builds on SysML v2 models, enriched with domain-specific libraries, to capture requirements, system concepts, and hardware/software abstractions. 

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Session: 4.11 Hardware Design - RISC-V Applications
Thu. March 12, 2026
11:45 - 12:15 PM PDT
Extending RISC-V into VLIW/SIMD Architectures for Application-Specific Workloads.
  • Gert Goossens
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The RISC-V ISA provides opcode space to encode custom instructions, typically operating on RISC-V’s register file. This can offer meaningful speedups. For higher performance, parallel processing is needed in the form of instruction-level parallelism (ILP) and data-level parallelism (DLP). We'll discuss the concepts for custom extensions to the RISC-V ISA, for application-specific workloads and illustrate the effectiveness of this approach with case studies.

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Agenda Exhibition & Conference