Synopsys Processor IP Summit 2025

Accelerate the future of mobility with RISC-V

As software-defined vehicles become a reality, embracing RISC-V enables the automotive industry to unlock a new era of innovation, collaboration and growth. With our commitment to making RISC-V the open standard for automotive, we are driving the development of a vibrant ecosystem that enables faster time-to-market, increased flexibility and improved cost control. Together with our partners, we are shaping the future of mobility.

Building on this vision, Infineon is the first semiconductor provider to announce the introduction of an automotive RISC-V microcontroller family. This new family will become part of our established AURIX™ brand and extend our existing portfolio, which includes solutions based on TriCore™ and ARM®. It will cater to a wide range of applications from entry-level to high-performance needs. Our RISC-V virtual prototype has been launched at Embedded World 2025. The starter kit is designed to enable pre-silicon software development and thus foster a comprehensive RISC-V software and tool ecosystem.

As the "brain" of the cockpit, SoCs have transitioned from providing basic computing and connectivity to delivering massive, efficient AI processing, heterogeneous architectures, and flexible software ecosystems. In this talk, we will discuss the shift of cockpits moving beyond passive functionality to active, personalized, and context-aware intelligence—redefining the in-vehicle experience. Looking ahead, SoCs will continue to be the cornerstone, driving cockpits toward even more intuitive, safe, and human-centric interactions. Demand for on-device AI computing has surged. Modern SoCs integrate dedicated AI accelerators (e.g., NPUs, DSPs) with massive parallel computing power, which ensures efficient allocation of computing resources, reducing latency and power consumption—critical for automotive-grade reliability.

As Generative AI moves to the edge, Neural Processing Units (NPUs), designed for compute intensive vision processing, are being tasked with additional requirements for Large Language Models (LLMs), including extremely large parameter sizes. This session explores the implementation challenges related to compute density, memory hierarchies, bandwidth and software toolchains for NPUs running GenAI workloads. Attendees will gain insights into how modern SoCs are being designed to use NPUs that support transformer-based models and multimodal GenAI at the edge.

Learn how Synopsys MetaWare MX’s Application Performance Model (APM) and Synopsys Platform Architect enable early, data-driven performance analysis and optimization of AI SoCs. This session demonstrates how the APM provides processor-level rapid benchmarking to identify bottlenecks and validate architectural decisions. This session also highlights how Platform Architect models, simulates, and analyzes system-level performance using real application traces and traffic profiles. 

With advanced computing systems increasingly defined and differentiated by software, SoCs must handle heterogenous workloads in the most efficient manner possible. This software-first approach enables continuous feature enhancements throughout a product’s lifecycle, whether the product is used in consumer devices, multi-sensory robotics, or software-defined vehicles. These highly integrated SoCs are powered by flexible, PPA-efficient processors capable of handling a diverse range of tasks—including future workloads unforeseen at the time of design. To meet these processing demands for data-intensive workloads like vision, radar, and AI/ML processing, leveraging vector operations is key. By processing data in vectors, these systems can achieve significant gains in efficiency, unlocking new levels of performance and adaptability for tomorrow’s software-driven innovations.

Electronics OEMs face a complex security landscape where the protection of intellectual property, customer data, customer trust, and infrastructure integrity must be weighed against cost and time-to-market pressures. As embedded systems become increasingly connected, vulnerabilities at any layer—from silicon through firmware —can jeopardize brand reputation and operational integrity. This presentation explores the cyber kill chain for modern electronics, the security technologies native to RISC-V, and a hardware rooted strategy to facilitate holistic security for OEM electronics and their customers.

Deploying models like LLMs and diffusion networks to edge devices is challenging due to their size and FP32 weight formats. This talk explores how MulticoreWare enables real-time inference on Synopsys ARC NPX NPU IP, achieving sub-500ms latency, through advanced software techniques such as pruning, quantization, distillation, and scheduling. Learn how expert optimization unlocks powerful AI capabilities on constrained edge devices.

More and more automotive processor suppliers are adopting the RISC-V architecture. For this to be successful, this push needs to be accompanied by a similar push to get existing, road-proven, and standardized automotive software running on this architecture. Bringing AUTOSAR to RISC-V, including its well-established safety mechanism, is therefore important. This presentation will discuss the high-level overview of the challenges and solutions faced when bringing AUTOSAR to RISC-V.

Industry consolidation and cost streamlining has channeled alignment to standardized instruction set architectures (ISAs) such as RISC-V. As Moore’s law slows, design teams seek different ways to deliver unique solutions for real-time applications while maintaining power, performance, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools, and software ecosystem, but look to extend the architecture to meet their product’s unique needs. This discussion will explore how Synopsys’ ARC-V processor implementations leveraging custom RISC-V extensions can enable designers to meet their unique real-time application requirements and provide SoC differentiation.

The automotive industry is experiencing a massive paradigm shift. Cars are becoming increasingly autonomous, connected, and computerized. Modern E/E-architectures require unforeseen functionality integration density based on the desire to reduce general electrification BoM. In this transition from classical to zonal approaches, RISC-V can be as regarded as an enabler considering unified HW-SW interface and optimization capabilities. However, designing smart zones is going notably beyond and require careful consideration of respective use-cases during design-time. The talk critically bridges the gap between enabling technologies and actual value proposition.

On the path to autonomous driving, vehicles with software-defined architectures are becoming mainstream.  The resulting advanced vehicle designs are influencing both the underlying hardware and software architectures:  system hardware implementations are transitioning from discrete ECUs to domain controllers to zonal controllers, while more software functions are being integrated on shared resources, requiring virtualized workloads and mixed-criticality support.  This panel will examine the future requirements of software-centric vehicles and RISC-V's role in that future.