The power delivery network is a critical part of any modern semiconductor device. Traditionally, power distribution competed with signal routing because the metal layers for both were on the frontside of the substrate. Distributing power on the backside and passing the power to the frontside with Nano TSVs (through-silicon vias) reduces congestion and improves performance, power, and area (PPA). PPA improves due to reduced IR droop and increased density from cell shrinkage made possible by reduced congestion on the frontside. This paper shows how a collaboration between Synopsys and Intel Foundry proved the value of Intel Foundry’s PowerVia backside power delivery on Intel 18A process node. We present data on wire length, routing, wire density, cell density, power, and thermal issues. In this work, the backside layer stack also includes the top-level clock tree network and other critical signals. Backside routing may be key to superior next-generation high-performance, AI, Automotive, Mobile and hyperscaler application chips.

Abstraction (which implies modelling, and characterization) has been the cornerstone of two revolutions in integrated circuits realization: polygon layout [1][2] in the ‘80s, and logic synthesis [3] in the ‘90s. We are at the dawn of another revolution: disaggregated (chiplet-based), heterogeneous (2.5D+ packaging) integration. The lack of a comprehensive modelling, and characterization solution may harm the adoption, and the deployment of chiplet-based systems.

Due to their inherent parallel search capability, content addressable memories (CAM) are an effective solution for numerous data-intensive applications such as network-routing, pattern matching, data mining and analytics, and neuromorphic associative memory. In this paper, we present multi-level FeFET CAM design solutions with enhanced storage capabilities. We first explore 2T complementary FeFET CAM design and evaluate its performance compared to its n-type counterparts for multi-bit cell storage. With process variations limiting the number of reliable FeFET programable states, we explore exploiting multi-level FeFETs using more transistors per cell and develop a multidimensional encoding scheme for enhanced cell storage. This work paves the way for denser storage and higher energy efficiency systems.

Quantum Computing Superconducting qubits and Superconducting sensors are Two-Level Systems (TLS) modeled in a double well potential.  Traditional bulk Density-Functional Theory (DFT) methods do not adequately capture the complete physics including key aspects and dynamics of superconductivity. Superconductivity at the atomistic level is inherently modeling quantum-mechanical properties, but complexity limits modeling at scale. In this paper we will describe the challenges of modeling and the simulation methods to describe the band structure of topological insulators and non-equilibrium Green function (NEGF) to compute the characteristics of interfaces for superconductivity, along with topological, and thermal properties.  The QuantumATK tool leverages density functional theory (DFT) with plane wave LCAO basis sets, semi-empirical methods, conventional Force Fields (FFs) and Machine Learning FFs (ML FFs).    In this paper we study the SIS junction to improve sensitivity, coherence and lifetime, of qubits and sensors, leveraging MLFFs to simulate 100,000 atom systems.

With the MOSFET characteristics improving dramatically at cryogenic temperatures, a plethora of design opportunities arise. In this work, we propose a novel 5T HalfSRAM design for cold CMOS physical unclonable function (PUF) applications. The 5T cell is area efficient and data remanenceaware and offers a versatile solution to SRAM type memories. The design Builds on the low leakage characteristics of cold CMOS and eliminates the need for voltage ramp-up and power-on/off cycles thereby evading pre- and post-erasure PUF attacks. We also propose bleeder designs for handling data remanence issues in traditional SRAM design solutions. The bleeder designs can be used jointly or independently and activate automatically without the need for external triggers thereby guarding against cold boot attacks. 

 The vast number of multiply and accumulate (MAC) operations used by artificial intelligence (AI) applications poses a challenge to the traditional Von Neumann architecture. Compute-inmemory (CIM) architectures have been proposed for accelerating MAC operations. There is a rising demand for flexible architectures that balance the model accuracy requirements and design performance efficiency. In this work, we propose a reconfigurable analog static random-access memory (SRAM)-based analog IMC macro design that supports 2, 3, and 4-bit precision for each of the input, weight, and output. We assess the design based on a 64x180 SRAM-CIM macro. Our macro achieves a normalized peak throughput of 13.8 TOPS, a normalized peak energy and area efficiencies of 292 TOPS/W and 166 TOPS/mm2 respectively.

In our GOMAC 2024 paper [1] we made the case for COLD and CRYO CMOS and FD-SOI for HPC. In this paper we will propose and present a STCO/DTCO design flow that expands on the traditional power*performance*area (PPA) optimization with the additional variable of cooling costs, to a   Power*Performance*Area*Cooling-cost design space co-optimization. We will use the results of our power and performance studies [1,2] and our detailed understanding of CMOS parameter behavior vs. temperature to propose a design space flow that optimizes operating VDD, operating temperature, performance and cooling costs and discuss the implications of that design space optimization on device engineering and on the design eco systems. The flow utilizes AI/ML to assign weights for variables as desired by the designer and a feedback loop for further refinement and filtering of viable solutions. However, in this paper we will focus on the basic concepts governing the DTCO / STCO design flow and not get to the AI / ML optimization process itself.

UCIe enables efficient interoperability between heterogeneous dies (chiplets) in a single package, while optimizing for power, performance, and latency. The latest spec version 2.0 builds on these capabilities with support for more advanced packaging, customized chiplet selection, manageability system architecture, higher bandwidth density and improved power efficiencies. The industry’s rapid adoption of UCIe for robust die-to-die connectivity is seen for a wide range of highly customized low-volume applications in high-performance computing and automotive domains, with important implications for government and defense applications. This paper will delve into the UCIe IP variants for standard and advanced packaging and how government and DIB designers can make performance and cost tradeoffs.  

As the semiconductor industry continually strives to meet the needs of Moore’s law, not only will the Silicon process and manufacturing need to improve, but the Electronic Design Automation (EDA) industry must enhance their tools and methodologies so designers can take advantage of the improvements. The introduction of the RibbonFET gate-all-around (GAA) transistor and the PowerVia backside power delivery in Intel 18A process represent the next major advancements in semiconductor technology. Intel Foundry and Synopsys collaborated to add new cutting-edge EDA tool technologies to Synopsys’ Fusion Compiler™ to maximize these advancements across a wide range of design styles and priorities.