Why Attend?

IMS is the flagship event in a week dedicated to all things microwaves and RF. The week also includes the IEEE MTT-S Radio Frequency Integrated Circuits Symposium (RFIC) and the Automatic Radio Frequency Techniques Group (ARFTG).

Synopsys at IMS

Visit Synopsys at IMS where we will be presenting our advanced solutions for RFIC design and Design Technology Co-Optimization (DTCO).

Panel Discussion

Session number - PL3

Date: 6/18/2024

Time: 12:00 - 1:30  PM

Location: 207AB

AI in RFIC Design: Opportunities, Threats, and Limitations

The growth in generative AI has, naturally, raised the question of its impact on RFIC design. The latter has been traditionally regarded as somewhat of a black art, requiring the ‘magic’ of human intuition and creativity. But is RFIC design really so, or will AI be able to automate large portions of the design process in the future? Are the days of hand-crafted RFIC design limited? Will AI replace design engineers or only augment their capabilities, to some extent? This lunch time panel, with both industry and academic experts, will attempt to unentangle the impact of AI in RFIC design.

MicroApps Session:

Session number - WEMA22

Date: 6/19/2024

Time: 3:30 - 3:45 PM

Room: MicroApps Theater, Booth 2159

mmWave CMOS Power Amplifier Design and Simulation with Custom Compiler and PrimeSim

CMOS technologies support FET devices with Ft and Fmax well beyond 400GHz, which make it possible to design RFICs operating in 5G mmWave and automotive Radar frequency bands.   We'll present the CMOS PA designs with Synopsys Custom Compiler and PrimeSim, along with the iPDKs from GlobalFoundries and TSMC process technology.   Custom Compiler is an OA-based EDA platform that can interoperate with existing schematic and layout designs in other EDA platforms.   PrimeSim supports both HSPICE and Spectre netlist formats for DC, S-parameter and Harmonic Balance simulations.  We'll discuss CMOS PA simulations including load-pull, Pout, PAE, and EVM.

MicroApps Session:

Session number - THMA11

Date: 6/20/2024

Time: 12:00 - 12:15 PM

Room - MicroApps Theater, Booth 2159

Design Technology Co-Optimization (DTCO) for RF Circuit with GaN-based Devices

Design Technology Co-Optimization (DTCO) integrated flows reduce development cycle time through a single environment for TCAD, SPICE, and circuit engineers that mitigates errors in the flow of information, and allows for best performance systems via mathematical optimization, or machine learning, with input parameters in device and interconnect design space, as well as layout floorplanning.
GaN HEMTs are leading candidates for high power amplifiers for 5G/6G base stations. However, GaN-based device technologies involve unintentional and intentionally introduced defect levels that present challenges beyond those in other semiconductor device technologies. Therefore, a DTCO flow approach is particularly suited for RF GaN systems.

Exhibit Booth #2354

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Exhibit Hours

  • Tuesday, 18 June 2024: 09:30-17:00
  • Wednesday, 19 June 2024: 09:30-18:00
  • Thursday, 20 June 2024: 09:30-15:00


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