USB Type-C Subsystem Verification Solution

Synopsys® VC USB Type-C™ Subsystem Verification Solution is a highly configurable verification environment with automated UVM test bench generation capabilities and comprehensive set of subsystem level verification features, enabling users to achieve accelerated verification closure of USB Type-C subsystem.

USB Type-C Subsystem Verification Solution


  • SystemVerilog/UVM
  • UVM Source code functional test suites
  • Complete subsystem verification solution
  • Multiple protocols can be enabled
  • Expandable to additional protocol support

Key Features

  • USB, USB PD and DisplayPort traffic on Type-C signals
  • Support USB Type-C connection state machine
  • Built-in sequence for mode discovery and entry
  • Provides optional voltage level modeling on Type-C CC 1/2 signals using SystemVerilog standard nettype