Highlights
- SystemVerilog/UVM
- UVM Source code functional test suites
- Complete subsystem verification solution
- Multiple protocols can be enabled
- Expandable to additional protocol support
Synopsys® VC USB Type-C™ Subsystem Verification Solution is a highly configurable verification environment with automated UVM test bench generation capabilities and comprehensive set of subsystem level verification features, enabling users to achieve accelerated verification closure of USB Type-C subsystem.