EDA
System
IP
SolvNetPlus
Training & Education
Architecture and Key Features
Specifications: USB4 V2, V1
Interfaces: PIPE 6/5/4/3 and Serial Interface Support
DUT Types/Topology: USB4 Subsystem, Router (Host/Device), PHY, Lane Adaptor and Retimer Cable/On-Board)
Key VIP Features
- Specification linked Functional coverages
- Dynamic Switching between Asymmetric & Symmetric modes
- USB 4.0 Stack – Logical, Transport, Configuration & Host Adapter Layer
- Extensive Error Injection and Sequence Collections
Debug and Analysis
- Router Path statistics
- Trace files and Verbose Controlled Logs
- Debug Ports in Waveform Dumps
- Advanced Debug mechanisms through predefined Switches
Key Protocol Features
- Adapters and Adapter Interface – USB, PCIe and Display Port
- Routing Function – BW Management, Flow Control and packet routing
- Multi-Port and Multi-Protocol Verification Testbench
- SideBand Interface
- Elaborate Programing Interface
- Inter/Intra Domain Scenarios
- TMU Support
Test Suites / Groups Features
- High Level of Automation Support provided with less worries about maintenance
- Testbench control provided through both compile time and run time defines
- VIP Configurations, prebuilt robust and exhaustive set of sequences and open-source tests
- Advanced Coverage Model with End-to-End Scoreboards
- Full Flexibility to user to extend existing's tests as per their custom requirements
- Plug‑and‑Play Framework for IP‑Level Verification and Testbench Migration from IP to SoC
Ask Synopsys
i
NOTICE: You are interacting with an AI-powered chatbot that provides general information about Synopsys, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by Synopsys and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.