About Universal Chiplet Interconnect Express

Synopsys Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) provides verification of design implementations based on latest UCIe specifications which can be used from IP to system level to accelerate verification closure. Synopsys VIP for UCIe enables verification for all topologies and at all signaling interfaces of a UCIe design: Flit aware Die-to-Die interface (FDI) between Protocol layer and Die to Die adapter, Raw Die-to-Die Interface (RDI) between Die-to-Die adapter and Physical layer, and Physical link interface between two dies - for single and multi-module chiplet setups. Synopsys VIP Test Suites, pre-built specification tied testcases, and SoC integration setups with IPs help accelerate your time to market with high quality deliverables.

Key Benefits

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Native SystemVerilog/UVM

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Source Code Test Suits Available

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Built-in Protocol Checks

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Complete Subsystem Verification Solution



  • Native SystemVerilog/UVM
  • Source code test
  • Built-in protocol checks
  • Verification plan and coverage
  • Synopsys Verdi protocol-aware debug
  • Runs on all major simulators



Specification Version

UCIe 1.0, 1.1

DUT Configuration

Full Stack, D2D Adapter, PHY

Protocol Mode

Streaming Mode, CXL Mode, 
PCIe Mode, Raw Format


Mainband, Sideband


Standard (LANES=16), 
Advanced (LANES=32, LANES=64) 

Module Configuration

Single, Multi module

Link Speeds

Up to 32GT/s

Link Width

x16, x32, x64, x128, x256

RDI Shim Layer

Interface to provide direct communication between US and DS RDI

RDI API Interface

To inject user-defined Sideband and Mainband packets at RDI interface (bypassing Die-to-Die Adapter and FDI)

RDI Mainband Width

16B, 32B, 64B, 128B, 256B

RDI Sideband Width

8 bits, 16 bits, 32 bits


Spec Defined registers (DVSEC, PHY/D2D)


FDI, RDI, Link

PHY Features

Link Initialization and training, Lane Repair, Lane Reversal, Clock Gating


Support and Training


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