Specifications: UCIe v1.0, v1.1, v2.0
Interfaces: FDI/RDI/PHY link
DUT Types/Topology
- D2D Adapter, Phy, Protocol, Full Stack
Key VIP Features
- CXL over UCIe, PCIe over UCIe, Streaming
- Modes of operation: Active, Passive
- API based transaction flow for ease of use
- Specification-linked protocol checks and functional coverage
- Exceptions, callbacks, error injection and analysis ports for Scoreboard
- RDI Shim layer at D2D adapter for early test development
- Configurable interpacket delays for mainband and sideband packets
Debug and Analysis
- Debug Ports: ASCII string for LTSM states, Scramble/unscramble data, LFSR Rx/Tx data, Rx/Tx pattern detected
- Multiple log options: UVM reporter, Transaction log
Available on SoC Verification Kit (SVK) for interoperability and subsystem/SoC level verification using Synopsys IP
Key Protocol Features
- Support for all Flit formats and Data Rates
- Support for mainband, sideband, and DLLP data width
- Standard and Advanced Package
- Multi module support: x2 and x4
- Clocking modes: Strobe, Continuous, Half rate and Quarter rate
- Parity feature, CRC, Retry
- Enhanced Multi-Protocol support
- Power Management Link States, Cross combination of state request
- Sideband MTP Support
- Compliance support (Flit Injection & retry)
- Repair feature support
- Link width degrade, Speed degrade
- Suports UCIe-S, SO, SPMO
- Scrambling/Descrambling, Lane Reversal, Retrain and Error recovery
Test Suites / Groups Features
- Test Groups based on the DUT Types: Full stack, D2D Adapter, Phy
- Control and status registers to enable software to test various combination of flows
- Hooks for DUT integration in Test Bench