Synopsys Webinar

The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power efficient and cost-efficient solutions.

UCIe 1.1 addresses four broad areas that encourage a thriving open chiplet ecosystem. These include enhancements like automotive segment, streaming protocol usages, cost optimization for advanced packages, and compliance testing.

This Synopsys webinar focuses on key design considerations to bring forward the verification requirements and an overview of the Synopsys verification solution to enable UCIe 1.1 complex designs.


Listed below are the industry leaders scheduled to speak.

Varun Agrawal

Sr Staff Product Manager

Varun has 15 years of experience in IP to System Level Functional Verification with expertise in Simulation, Emulation and Virtualization domain. Prior to Product Management, Varun led R&D projects in Virtualization over Emulation and worked in various development and customer facing roles at multiple design and EDA companies. He holds Bachelors in Electronics and Communication from NIT Hamirpur, India, and MBA in International Marketing from India Institute of Foreign Trade (IIFT), New Delhi, India.

Divya Jindal

Product Engineer

Divya Jindal is a Product Engineer for UCIe VIP with 7+ years of experience working on Verification solutions for Memory protocols and UCIe. Divya is working on Synopsys UCIe IP for in-house validation.

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